| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 690 SEXTLOAD, enumerator
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| D | SelectionDAGNodes.h | 1877 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 624 LD->getExtensionType() == ISD::SEXTLOAD) { in SelectIndexedLoad()
860 LD->getExtensionType() != ISD::SEXTLOAD || in SelectMul()
886 LD->getExtensionType() != ISD::SEXTLOAD || in SelectMul()
1040 LD->getExtensionType() != ISD::SEXTLOAD || in SelectTruncate()
1065 LD->getExtensionType() != ISD::SEXTLOAD || in SelectTruncate()
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| D | HexagonISelLowering.cpp | 651 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
1303 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 303 Extension = ISD::SEXTLOAD; in SelectToLitPool()
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 79 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom); in R600TargetLowering()
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom); in R600TargetLowering()
1176 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) { in LowerLOAD()
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| D | SIISelLowering.cpp | 86 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand); in SITargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 449 case ISD::SEXTLOAD: OS << ", sext"; break; in print_details()
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| D | DAGCombiner.cpp | 2763 if (LN0->getExtensionType() != ISD::SEXTLOAD && in visitAND()
4463 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { in visitSIGN_EXTEND()
4470 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, in visitSIGN_EXTEND()
4493 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { in visitSIGN_EXTEND()
4494 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, in visitSIGN_EXTEND()
4515 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && in visitSIGN_EXTEND()
4525 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT, in visitSIGN_EXTEND()
4789 if (LN0->getExtensionType() != ISD::SEXTLOAD) { in visitZERO_EXTEND()
5137 ExtType = ISD::SEXTLOAD; in ReduceLoadWidth()
5176 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) in ReduceLoadWidth()
[all …]
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| D | LegalizeVectorOps.cpp | 481 case ISD::SEXTLOAD: in ExpandLoad()
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| D | LegalizeDAG.cpp | 957 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
1091 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; in LegalizeLoadOps()
1116 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
3573 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, in ExpandNode()
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| D | LegalizeIntegerTypes.cpp | 1819 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1891 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1027 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select()
1061 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select()
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| D | PPCISelLowering.cpp | 80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in PPCTargetLowering()
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in PPCTargetLowering()
439 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); in PPCTargetLowering()
1268 LD->getExtensionType() == ISD::SEXTLOAD && in getPreIndexedAddressParts()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 193 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in NVPTXTargetLowering()
1481 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
1614 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
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| D | NVPTXISelDAGToDAG.cpp | 239 if ((LD->getExtensionType() == ISD::SEXTLOAD)) in SelectLoad()
468 if (ExtensionType == ISD::SEXTLOAD) in SelectLoadVector()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 182 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in SystemZTargetLowering()
959 if (Load->getExtensionType() == ISD::SEXTLOAD) { in adjustSubwordCmp()
997 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD; in adjustSubwordCmp()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 65 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); in MipsSETargetLowering()
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| D | MipsISelLowering.cpp | 228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
382 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); in MipsTargetLowering()
1408 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, in lowerBR_JT()
2013 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || in lowerLOAD()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in XCoreTargetLowering()
133 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 459 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; in LowerFormalArguments_32()
1253 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in SparcTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1483 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) in SelectARMIndexedLoad()
1487 if (LD->getExtensionType() == ISD::SEXTLOAD) { in SelectARMIndexedLoad()
1536 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; in SelectT2IndexedLoad()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | CodeGenPrepare.cpp | 1717 LType = ISD::SEXTLOAD; in MoveExtToFormExtLoad()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 619 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
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