| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitTFRCondSets.cpp | 99 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction() local
117 if (DestReg != SrcReg2) { in runOnMachineFunction()
119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
156 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction() local
172 if (DestReg != SrcReg2) { in runOnMachineFunction()
175 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
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| D | HexagonInstrInfo.h | 72 unsigned &SrcReg, unsigned &SrcReg2,
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| D | HexagonInstrInfo.cpp | 338 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
392 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
402 SrcReg2 = 0; in analyzeCompare()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 381 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
383 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
385 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
389 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 383 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ? in fuseCompareAndBranch() local
388 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareAndBranch()
418 if (SrcReg2) in fuseCompareAndBranch()
419 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareAndBranch()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 206 unsigned &SrcReg, unsigned &SrcReg2,
210 unsigned SrcReg, unsigned SrcReg2,
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| D | PPCInstrInfo.cpp | 1057 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
1068 SrcReg2 = 0; in analyzeCompare()
1079 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
1085 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
1186 if (SrcReg2 != 0) in optimizeCompareInstr()
1225 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1226 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1272 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 393 unsigned &SrcReg2,
400 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | X86InstrInfo.cpp | 2153 unsigned SrcReg2; in convertToThreeAddress() local
2156 SrcReg2, isKill2, isUndef2, ImplicitOp2)) in convertToThreeAddress()
2166 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
2173 LV->replaceKillInstruction(SrcReg2, MI, NewMI); in convertToThreeAddress()
3156 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
3168 SrcReg2 = 0; in analyzeCompare()
3178 SrcReg2 = 0; in analyzeCompare()
3187 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
3199 SrcReg2 = 0; in analyzeCompare()
3208 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 195 unsigned &SrcReg2, int &CmpMask,
203 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | ARMFastISel.cpp | 1481 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1483 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1484 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1492 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1493 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1500 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1805 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1806 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1811 .addReg(SrcReg1).addReg(SrcReg2)); in SelectBinaryIntOp()
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| D | ARMBaseInstrInfo.cpp | 1952 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
1959 SrcReg2 = 0; in analyzeCompare()
1966 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
1973 SrcReg2 = 0; in analyzeCompare()
2036 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
2043 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2044 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2066 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
2103 if (SrcReg2 != 0) in optimizeCompareInstr()
2131 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 738 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
747 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2) in emit3() argument
95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2) in emit3() argument
95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
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