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Searched refs:VReg (Results 1 – 23 of 23) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DLiveIntervalUnion.h119 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query() argument
120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query()
135 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init() argument
136 assert(VReg && LIU && "Invalid arguments"); in init()
137 if (UserTag == UTag && VirtReg == VReg && in init()
144 VirtReg = VReg; in init()
162 bool isSeenInterference(LiveInterval *VReg) const;
DMachineRegisterInfo.h503 unsigned getLiveInPhysReg(unsigned VReg) const;
/external/llvm/lib/CodeGen/
DLiveIntervalUnion.cpp149 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
150 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs()
151 RecentReg = VReg; in collectInterferingVRegs()
152 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
DMachineFunction.cpp426 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local
427 if (VReg) { in addLiveIn()
428 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!"); in addLiveIn()
429 return VReg; in addLiveIn()
431 VReg = MRI.createVirtualRegister(RC); in addLiveIn()
432 MRI.addLiveIn(PReg, VReg); in addLiveIn()
433 return VReg; in addLiveIn()
DLiveRangeEdit.cpp34 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
39 LiveInterval &LI = LIS.getOrCreateInterval(VReg); in createFrom()
DTailDuplication.cpp231 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local
232 SSAUpdate.Initialize(VReg); in TailDuplicateAndUpdate()
236 MachineInstr *DefMI = MRI->getVRegDef(VReg); in TailDuplicateAndUpdate()
240 SSAUpdate.AddAvailableValue(DefBB, VReg); in TailDuplicateAndUpdate()
245 SSAUpdateVals.find(VReg); in TailDuplicateAndUpdate()
253 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg); in TailDuplicateAndUpdate()
DMachineRegisterInfo.cpp347 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { in getLiveInPhysReg()
349 if (I->second == VReg) in getLiveInPhysReg()
DRegAllocFast.cpp186 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp272 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local
275 if (!VReg) { in getVR()
278 VReg = MRI->createVirtualRegister(RC); in getVR()
281 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
282 return VReg; in getVR()
305 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
306 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); in AddRegisterOperand()
320 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
323 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
324 VReg = NewVReg; in AddRegisterOperand()
[all …]
DInstrEmitter.h87 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp561 unsigned VReg = 0; in eliminateFrameIndex() local
657 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); in eliminateFrameIndex()
662 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, in eliminateFrameIndex()
665 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); in eliminateFrameIndex()
669 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII, in eliminateFrameIndex()
672 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true); in eliminateFrameIndex()
DARMISelLowering.cpp2811 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in StoreByValRegs() local
2812 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in StoreByValRegs()
/external/llvm/lib/Target/NVPTX/InstPrinter/
DNVPTXInstPrinter.cpp68 unsigned VReg = RegNo & 0x0FFFFFFF; in printRegName() local
69 OS << VReg; in printRegName()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2099 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_32SVR4() local
2100 if (!VReg) in LowerFormalArguments_32SVR4()
2101 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_32SVR4()
2103 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); in LowerFormalArguments_32SVR4()
2118 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_32SVR4() local
2119 if (!VReg) in LowerFormalArguments_32SVR4()
2120 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); in LowerFormalArguments_32SVR4()
2122 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_32SVR4()
2289 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
2290 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); in LowerFormalArguments_64SVR4()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32() local
394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
395 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_32()
505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32() local
506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); in LowerFormalArguments_32()
507 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments_32()
556 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64() local
558 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments_64()
627 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64() local
628 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); in LowerFormalArguments_64()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp1019 unsigned VReg = MI->getOperand(0).getReg(); in AdjustInstrPostInstrSelection() local
1034 MRI.setRegClass(VReg, RC); in AdjustInstrPostInstrSelection()
1076 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); in CreateLiveInRegister() local
1079 cast<RegisterSDNode>(VReg)->getReg(), VT); in CreateLiveInRegister()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp858 unsigned VReg = in LowerFormalArguments() local
860 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
861 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
863 unsigned VReg = in LowerFormalArguments() local
865 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
866 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1119 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments() local
1120 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1121 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
1172 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments() local
1173 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
1174 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerCCCArguments()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp351 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); in LowerCCCArguments() local
352 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
353 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp623 unsigned VReg = MRI.createVirtualRegister(RC); in LowerFormalArguments() local
624 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
625 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); in LowerFormalArguments()
674 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I], in LowerFormalArguments() local
676 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64); in LowerFormalArguments()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp767 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in addLiveIn() local
768 MF.getRegInfo().addLiveIn(PReg, VReg); in addLiveIn()
769 return VReg; in addLiveIn()
3375 unsigned VReg = addLiveIn(MF, ArgReg, RC); in copyByValRegs() local
3379 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp900 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass); in SaveVarArgRegisters() local
901 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); in SaveVarArgRegisters()
919 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i], in SaveVarArgRegisters() local
921 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128); in SaveVarArgRegisters()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp2346 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], in LowerFormalArguments() local
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments()
2373 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], in LowerFormalArguments() local
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); in LowerFormalArguments()