| /external/llvm/lib/CodeGen/ |
| D | RegAllocBase.cpp | 101 << MRI->getRegClass(VirtReg->reg)->getName() in allocatePhysRegs()
122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| D | PeepholeOptimizer.cpp | 164 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
269 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
363 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def)) in optimizeBitcastInstr()
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| D | VirtRegMap.cpp | 102 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
123 << MRI->getRegClass(Reg)->getName() << "\n"; in print()
131 << "] " << MRI->getRegClass(Reg)->getName() << "\n"; in print()
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| D | AllocationOrder.cpp | 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| D | TargetInstrInfo.cpp | 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo
54 return TRI->getRegClass(RegClass); in getRegClass()
326 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); in canFoldCopy()
331 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()
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| D | TargetRegisterInfo.cpp | 89 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); in getAllocatableClass()
158 return TRI->getRegClass(I + countTrailingZeros(Common)); in firstCommonClass()
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| D | RegisterPressure.cpp | 52 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in increase()
68 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in decrease()
119 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]); in increaseRegPressure()
136 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]); in decreaseRegPressure()
331 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in initLiveThru()
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| D | MachineSink.cpp | 135 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
506 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) in FindSuccToSinkTo()
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| D | LiveRangeEdit.cpp | 34 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom()
399 << MRI.getRegClass(LI.reg)->getName() << '\n'); in calculateRegClassAndHint()
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| D | MachineRegisterInfo.cpp | 52 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
68 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
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| D | RegisterCoalescer.cpp | 284 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); in setRegisters()
287 } else if (!MRI.getRegClass(Src)->contains(Dst)) { in setRegisters()
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters()
293 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters()
651 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) in removeCopyByCommutingDef()
774 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef()
824 RCForInst = TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), DefRC, in reMaterializeTrivialDef()
2240 << MRI->getRegClass(Reg)->getName() << '\n'); in runOnMachineFunction()
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| D | OptimizePHIs.cpp | 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
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| D | TailDuplication.cpp | 285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in TailDuplicateAndUpdate()
394 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in ProcessPHI()
431 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in DuplicateInstruction()
441 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg)); in DuplicateInstruction()
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| D | InlineSpiller.cpp | 730 MRI.getRegClass(SVI.SpillReg), &TRI); in hoistSpill()
1116 MRI.getRegClass(NewLI.reg), &TRI); in insertReload()
1134 MRI.getRegClass(NewLI.reg), &TRI); in insertSpill()
1259 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); in spillAll()
1310 << MRI.getRegClass(edit.getReg())->getName() in spill()
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| D | RegAllocGreedy.cpp | 600 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
601 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
699 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); in tryEvict()
1044 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1311 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1362 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg))) in tryInstructionSplit()
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| D | CalcSpillWeights.cpp | 82 const TargetRegisterClass *rc = mri.getRegClass(reg); in copyHint()
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| D | Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg); in trivialSpillEverywhere()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
161 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
220 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
238 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
319 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); in AddRegisterOperand()
426 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
485 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
536 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
577 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
594 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
283 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
541 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) { in optimizeAllLanesPattern()
557 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
563 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 36 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg()
37 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg()
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 117 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in inferRegClass()
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| D | AMDGPUInstrInfo.cpp | 237 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); in convertToISA()
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| D | SIISelLowering.cpp | 688 return MRI.getRegClass(Reg); in getRegClassForNode()
698 return TRI.getRegClass(OpClassID); in getRegClassForNode()
712 return TRI.getRegClass(OpClassID); in getRegClassForNode()
721 return TRI.getRegClass( in getRegClassForNode()
736 return TRI->getRegClass(RegClass)->hasSubClassEq(RC); in fitsRegClass()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.h | 125 return *getRegBank().getRegClass(R); in getRegisterClass()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 445 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
481 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
514 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
515 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
517 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
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