1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ASM_ARCH_OMAP_HARDWARE_H 20 #define __ASM_ARCH_OMAP_HARDWARE_H 21 #include <asm/sizes.h> 22 #ifndef __ASSEMBLER__ 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <asm/types.h> 25 #include <asm/arch/cpu.h> 26 #endif 27 #include <asm/arch/io.h> 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #include <asm/arch/serial.h> 30 #define OMAP_MPU_TIMER1_BASE (0xfffec500) 31 #define OMAP_MPU_TIMER2_BASE (0xfffec600) 32 #define OMAP_MPU_TIMER3_BASE (0xfffec700) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define MPU_TIMER_FREE (1 << 6) 35 #define MPU_TIMER_CLOCK_ENABLE (1 << 5) 36 #define MPU_TIMER_AR (1 << 1) 37 #define MPU_TIMER_ST (1 << 0) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define CLKGEN_REG_BASE (0xfffece00) 40 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) 41 #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) 42 #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) 45 #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) 46 #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) 47 #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) 50 #define CK_RATEF 1 51 #define CK_IDLEF 2 52 #define CK_ENABLEF 4 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define CK_SELECTF 8 55 #define SETARM_IDLE_SHIFT 56 #define DPLL_CTL (0xfffecf00) 57 #define DSP_CONFIG_REG_BASE (0xe1008000) 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) 60 #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 61 #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 62 #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define ULPD_REG_BASE (0xfffe0800) 65 #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) 66 #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) 67 #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define DIS_USB_PVCI_CLK (1 << 5) 70 #define USB_MCLK_EN (1 << 4) 71 #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) 72 #define SOFT_UDC_REQ (1 << 4) 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define SOFT_USB_CLK_REQ (1 << 3) 75 #define SOFT_DPLL_REQ (1 << 0) 76 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) 77 #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) 80 #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) 81 #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) 82 #define DIS_MMC2_DPLL_REQ (1 << 11) 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define DIS_MMC1_DPLL_REQ (1 << 10) 85 #define DIS_UART3_DPLL_REQ (1 << 9) 86 #define DIS_UART2_DPLL_REQ (1 << 8) 87 #define DIS_UART1_DPLL_REQ (1 << 7) 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define DIS_USB_HOST_DPLL_REQ (1 << 6) 90 #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) 91 #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) 92 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) 95 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) 96 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) 97 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define MOD_CONF_CTRL_0 0xfffe1080 100 #define MOD_CONF_CTRL_1 0xfffe1110 101 #define FUNC_MUX_CTRL_0 0xfffe1000 102 #define FUNC_MUX_CTRL_1 0xfffe1004 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define FUNC_MUX_CTRL_2 0xfffe1008 105 #define COMP_MODE_CTRL_0 0xfffe100c 106 #define FUNC_MUX_CTRL_3 0xfffe1010 107 #define FUNC_MUX_CTRL_4 0xfffe1014 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define FUNC_MUX_CTRL_5 0xfffe1018 110 #define FUNC_MUX_CTRL_6 0xfffe101C 111 #define FUNC_MUX_CTRL_7 0xfffe1020 112 #define FUNC_MUX_CTRL_8 0xfffe1024 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define FUNC_MUX_CTRL_9 0xfffe1028 115 #define FUNC_MUX_CTRL_A 0xfffe102C 116 #define FUNC_MUX_CTRL_B 0xfffe1030 117 #define FUNC_MUX_CTRL_C 0xfffe1034 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define FUNC_MUX_CTRL_D 0xfffe1038 120 #define PULL_DWN_CTRL_0 0xfffe1040 121 #define PULL_DWN_CTRL_1 0xfffe1044 122 #define PULL_DWN_CTRL_2 0xfffe1048 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define PULL_DWN_CTRL_3 0xfffe104c 125 #define PULL_DWN_CTRL_4 0xfffe10ac 126 #define FUNC_MUX_CTRL_E 0xfffe1090 127 #define FUNC_MUX_CTRL_F 0xfffe1094 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define FUNC_MUX_CTRL_10 0xfffe1098 130 #define FUNC_MUX_CTRL_11 0xfffe109c 131 #define FUNC_MUX_CTRL_12 0xfffe10a0 132 #define PU_PD_SEL_0 0xfffe10b4 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define PU_PD_SEL_1 0xfffe10b8 135 #define PU_PD_SEL_2 0xfffe10bc 136 #define PU_PD_SEL_3 0xfffe10c0 137 #define PU_PD_SEL_4 0xfffe10c4 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define OMAP_TIMER32K_BASE 0xFFFBC400 140 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 141 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) 142 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) 145 #define MPUI_BASE (0xfffec900) 146 #define MPUI_CTRL (MPUI_BASE + 0x0) 147 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) 150 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) 151 #define MPUI_STATUS_REG (MPUI_BASE + 0x10) 152 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14) 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) 155 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) 156 #define OMAP_LPG1_BASE 0xfffbd000 157 #define OMAP_LPG2_BASE 0xfffbd800 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) 160 #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) 161 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) 162 #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define OMAP_PWL_BASE 0xfffb5800 165 #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) 166 #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) 167 #include "omap730.h" 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #include "omap1510.h" 170 #include "omap24xx.h" 171 #include "omap16xx.h" 172 #ifndef __ASSEMBLER__ 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #endif 175 #endif 176