1 /*
2 * linux/include/asm-arm/arch-omap/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * NOTE: Please use the following naming style for new pin entries.
26 * For example, W8_1610_MMC2_DAT0, where:
27 * - W8 = ball
28 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
29 * - MMC2_DAT0 = function
30 *
31 * Change log:
32 * Added entry for the I2C interface. (02Feb 2004)
33 * Copyright (C) 2004 Texas Instruments
34 *
35 * Added entry for the keypad and uwire CS1. (09Mar 2004)
36 * Copyright (C) 2004 Texas Instruments
37 *
38 */
39
40 #ifndef __ASM_ARCH_MUX_H
41 #define __ASM_ARCH_MUX_H
42
43 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
44 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
45
46 #ifdef CONFIG_OMAP_MUX_DEBUG
47 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
48 .mux_reg = FUNC_MUX_CTRL_##reg, \
49 .mask_offset = mode_offset, \
50 .mask = mode,
51
52 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
53 .pull_reg = PULL_DWN_CTRL_##reg, \
54 .pull_bit = bit, \
55 .pull_val = status,
56
57 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
58 .pu_pd_reg = PU_PD_SEL_##reg, \
59 .pu_pd_val = status,
60
61 #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
62 .mux_reg = OMAP730_IO_CONF_##reg, \
63 .mask_offset = mode_offset, \
64 .mask = mode,
65
66 #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
67 .pull_reg = OMAP730_IO_CONF_##reg, \
68 .pull_bit = bit, \
69 .pull_val = status,
70
71 #else
72
73 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
74 .mask_offset = mode_offset, \
75 .mask = mode,
76
77 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
78 .pull_bit = bit, \
79 .pull_val = status,
80
81 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
82 .pu_pd_val = status,
83
84 #define MUX_REG_730(reg, mode_offset, mode) \
85 .mux_reg = OMAP730_IO_CONF_##reg, \
86 .mask_offset = mode_offset, \
87 .mask = mode,
88
89 #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
90 .pull_bit = bit, \
91 .pull_val = status,
92
93 #endif /* CONFIG_OMAP_MUX_DEBUG */
94
95 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
96 pull_reg, pull_bit, pull_status, \
97 pu_pd_reg, pu_pd_status, debug_status) \
98 { \
99 .name = desc, \
100 .debug = debug_status, \
101 MUX_REG(mux_reg, mode_offset, mode) \
102 PULL_REG(pull_reg, pull_bit, !pull_status) \
103 PU_PD_REG(pu_pd_reg, pu_pd_status) \
104 },
105
106
107 /*
108 * OMAP730 has a slightly different config for the pin mux.
109 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
110 * not the FUNC_MUX_CTRL_x regs from hardware.h
111 * - for pull-up/down, only has one enable bit which is is in the same register
112 * as mux config
113 */
114 #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
115 pull_bit, pull_status, debug_status)\
116 { \
117 .name = desc, \
118 .debug = debug_status, \
119 MUX_REG_730(mux_reg, mode_offset, mode) \
120 PULL_REG_730(mux_reg, pull_bit, pull_status) \
121 PU_PD_REG(NA, 0) \
122 },
123
124 #define MUX_CFG_24XX(desc, reg_offset, mode, \
125 pull_en, pull_mode, dbg) \
126 { \
127 .name = desc, \
128 .debug = dbg, \
129 .mux_reg = reg_offset, \
130 .mask = mode, \
131 .pull_val = pull_en, \
132 .pu_pd_val = pull_mode, \
133 },
134
135
136 #define PULL_DISABLED 0
137 #define PULL_ENABLED 1
138
139 #define PULL_DOWN 0
140 #define PULL_UP 1
141
142 struct pin_config {
143 char *name;
144 unsigned char busy;
145 unsigned char debug;
146
147 const char *mux_reg_name;
148 const unsigned int mux_reg;
149 const unsigned char mask_offset;
150 const unsigned char mask;
151
152 const char *pull_name;
153 const unsigned int pull_reg;
154 const unsigned char pull_val;
155 const unsigned char pull_bit;
156
157 const char *pu_pd_name;
158 const unsigned int pu_pd_reg;
159 const unsigned char pu_pd_val;
160 };
161
162 enum omap730_index {
163 /* OMAP 730 keyboard */
164 E2_730_KBR0,
165 J7_730_KBR1,
166 E1_730_KBR2,
167 F3_730_KBR3,
168 D2_730_KBR4,
169 AA20_730_KBR5,
170 V17_730_KBR6,
171 C2_730_KBC0,
172 D3_730_KBC1,
173 E4_730_KBC2,
174 F4_730_KBC3,
175 E3_730_KBC4,
176
177 /* USB */
178 AA17_730_USB_DM,
179 W16_730_USB_PU_EN,
180 W17_730_USB_VBUSI,
181
182 /* Tornado LCD */
183 V19_730_GPIO_15,
184 M19_730_GPIO_77,
185 C21_730_GPIO_121_122,
186 K19_730_GPIO_126,
187 K15_730_GPIO_127,
188
189 P15_730_GPIO_16_17,
190
191 /* Tornado Navi */
192 M15_730_GPIO_83,
193 N20_730_GPIO_82,
194 N18_730_GPIO_81,
195 N19_730_GPIO_80,
196 L15_730_GPIO_76,
197
198 /* UART1 can go over it's normal pins or be redirected to the USB pins */
199 UART1_CTS_RTS,
200 OMAP_730_GPIOS_42_43, /* UART1 CTS, RTS lines as a GPIOs 42, 43 */
201 UART1_TX_RX,
202 OMAP_730_GPIOS_40_41, /* UART1 TX, RX lines as a GPIOs 40, 41 */
203 UART1_USB_RX_TX,
204 UART1_USB_RTS,
205 UART1_USB_CTS
206 };
207
208 enum omap1xxx_index {
209 /* UART1 (BT_UART_GATING)*/
210 UART1_TX = 0,
211 UART1_RTS,
212
213 /* UART2 (COM_UART_GATING)*/
214 UART2_TX,
215 UART2_RX,
216 UART2_CTS,
217 UART2_RTS,
218
219 /* UART3 (GIGA_UART_GATING) */
220 UART3_TX,
221 UART3_RX,
222 UART3_CTS,
223 UART3_RTS,
224 UART3_CLKREQ,
225 UART3_BCLK, /* 12MHz clock out */
226 Y15_1610_UART3_RTS,
227
228 /* PWT & PWL */
229 PWT,
230 PWL,
231
232 /* USB master generic */
233 R18_USB_VBUS,
234 R18_1510_USB_GPIO0,
235 W4_USB_PUEN,
236 W4_USB_CLKO,
237 W4_USB_HIGHZ,
238 W4_GPIO58,
239
240 /* USB1 master */
241 USB1_SUSP,
242 USB1_SEO,
243 W13_1610_USB1_SE0,
244 USB1_TXEN,
245 USB1_TXD,
246 USB1_VP,
247 USB1_VM,
248 USB1_RCV,
249 USB1_SPEED,
250 R13_1610_USB1_SPEED,
251 R13_1710_USB1_SE0,
252
253 /* USB2 master */
254 USB2_SUSP,
255 USB2_VP,
256 USB2_TXEN,
257 USB2_VM,
258 USB2_RCV,
259 USB2_SEO,
260 USB2_TXD,
261
262 /* OMAP-1510 GPIO */
263 R18_1510_GPIO0,
264 R19_1510_GPIO1,
265 M14_1510_GPIO2,
266
267 /* OMAP1610 GPIO */
268 P18_1610_GPIO3,
269 Y15_1610_GPIO17,
270
271 /* OMAP-1710 GPIO */
272 R18_1710_GPIO0,
273 V2_1710_GPIO10,
274 N21_1710_GPIO14,
275 W15_1710_GPIO40,
276
277 /* MPUIO */
278 MPUIO2,
279 N15_1610_MPUIO2,
280 MPUIO4,
281 MPUIO5,
282 T20_1610_MPUIO5,
283 W11_1610_MPUIO6,
284 V10_1610_MPUIO7,
285 W11_1610_MPUIO9,
286 V10_1610_MPUIO10,
287 W10_1610_MPUIO11,
288 E20_1610_MPUIO13,
289 U20_1610_MPUIO14,
290 E19_1610_MPUIO15,
291
292 /* MCBSP2 */
293 MCBSP2_CLKR,
294 MCBSP2_CLKX,
295 MCBSP2_DR,
296 MCBSP2_DX,
297 MCBSP2_FSR,
298 MCBSP2_FSX,
299
300 /* MCBSP3 */
301 MCBSP3_CLKX,
302
303 /* Misc ballouts */
304 BALLOUT_V8_ARMIO3,
305 N20_HDQ,
306
307 /* OMAP-1610 MMC2 */
308 W8_1610_MMC2_DAT0,
309 V8_1610_MMC2_DAT1,
310 W15_1610_MMC2_DAT2,
311 R10_1610_MMC2_DAT3,
312 Y10_1610_MMC2_CLK,
313 Y8_1610_MMC2_CMD,
314 V9_1610_MMC2_CMDDIR,
315 V5_1610_MMC2_DATDIR0,
316 W19_1610_MMC2_DATDIR1,
317 R18_1610_MMC2_CLKIN,
318
319 /* OMAP-1610 External Trace Interface */
320 M19_1610_ETM_PSTAT0,
321 L15_1610_ETM_PSTAT1,
322 L18_1610_ETM_PSTAT2,
323 L19_1610_ETM_D0,
324 J19_1610_ETM_D6,
325 J18_1610_ETM_D7,
326
327 /* OMAP16XX GPIO */
328 P20_1610_GPIO4,
329 V9_1610_GPIO7,
330 W8_1610_GPIO9,
331 N20_1610_GPIO11,
332 N19_1610_GPIO13,
333 P10_1610_GPIO22,
334 V5_1610_GPIO24,
335 AA20_1610_GPIO_41,
336 W19_1610_GPIO48,
337 M7_1610_GPIO62,
338 V14_16XX_GPIO37,
339 R9_16XX_GPIO18,
340 L14_16XX_GPIO49,
341
342 /* OMAP-1610 uWire */
343 V19_1610_UWIRE_SCLK,
344 U18_1610_UWIRE_SDI,
345 W21_1610_UWIRE_SDO,
346 N14_1610_UWIRE_CS0,
347 P15_1610_UWIRE_CS3,
348 N15_1610_UWIRE_CS1,
349
350 /* OMAP-1610 SPI */
351 U19_1610_SPIF_SCK,
352 U18_1610_SPIF_DIN,
353 P20_1610_SPIF_DIN,
354 W21_1610_SPIF_DOUT,
355 R18_1610_SPIF_DOUT,
356 N14_1610_SPIF_CS0,
357 N15_1610_SPIF_CS1,
358 T19_1610_SPIF_CS2,
359 P15_1610_SPIF_CS3,
360
361 /* OMAP-1610 Flash */
362 L3_1610_FLASH_CS2B_OE,
363 M8_1610_FLASH_CS2B_WE,
364
365 /* First MMC */
366 MMC_CMD,
367 MMC_DAT1,
368 MMC_DAT2,
369 MMC_DAT0,
370 MMC_CLK,
371 MMC_DAT3,
372
373 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
374 M15_1710_MMC_CLKI,
375 P19_1710_MMC_CMDDIR,
376 P20_1710_MMC_DATDIR0,
377
378 /* OMAP-1610 USB0 alternate pin configuration */
379 W9_USB0_TXEN,
380 AA9_USB0_VP,
381 Y5_USB0_RCV,
382 R9_USB0_VM,
383 V6_USB0_TXD,
384 W5_USB0_SE0,
385 V9_USB0_SPEED,
386 V9_USB0_SUSP,
387
388 /* USB2 */
389 W9_USB2_TXEN,
390 AA9_USB2_VP,
391 Y5_USB2_RCV,
392 R9_USB2_VM,
393 V6_USB2_TXD,
394 W5_USB2_SE0,
395
396 /* 16XX UART */
397 R13_1610_UART1_TX,
398 V14_16XX_UART1_RX,
399 R14_1610_UART1_CTS,
400 AA15_1610_UART1_RTS,
401 R9_16XX_UART2_RX,
402 L14_16XX_UART3_RX,
403
404 /* I2C OMAP-1610 */
405 I2C_SCL,
406 I2C_SDA,
407
408 /* Keypad */
409 F18_1610_KBC0,
410 D20_1610_KBC1,
411 D19_1610_KBC2,
412 E18_1610_KBC3,
413 C21_1610_KBC4,
414 G18_1610_KBR0,
415 F19_1610_KBR1,
416 H14_1610_KBR2,
417 E20_1610_KBR3,
418 E19_1610_KBR4,
419 N19_1610_KBR5,
420
421 /* Power management */
422 T20_1610_LOW_PWR,
423
424 /* MCLK Settings */
425 V5_1710_MCLK_ON,
426 V5_1710_MCLK_OFF,
427 R10_1610_MCLK_ON,
428 R10_1610_MCLK_OFF,
429
430 /* CompactFlash controller */
431 P11_1610_CF_CD2,
432 R11_1610_CF_IOIS16,
433 V10_1610_CF_IREQ,
434 W10_1610_CF_RESET,
435 W11_1610_CF_CD1,
436 };
437
438 enum omap24xx_index {
439 /* 24xx I2C */
440 M19_24XX_I2C1_SCL,
441 L15_24XX_I2C1_SDA,
442 J15_24XX_I2C2_SCL,
443 H19_24XX_I2C2_SDA,
444
445 /* 24xx Menelaus interrupt */
446 W19_24XX_SYS_NIRQ,
447
448 /* 24xx clock */
449 W14_24XX_SYS_CLKOUT,
450
451 /* 24xx GPMC wait pin monitoring */
452 L3_GPMC_WAIT0,
453 N7_GPMC_WAIT1,
454 M1_GPMC_WAIT2,
455 P1_GPMC_WAIT3,
456
457 /* 242X McBSP */
458 Y15_24XX_MCBSP2_CLKX,
459 R14_24XX_MCBSP2_FSX,
460 W15_24XX_MCBSP2_DR,
461 V15_24XX_MCBSP2_DX,
462
463 /* 24xx GPIO */
464 M21_242X_GPIO11,
465 AA10_242X_GPIO13,
466 AA6_242X_GPIO14,
467 AA4_242X_GPIO15,
468 Y11_242X_GPIO16,
469 AA12_242X_GPIO17,
470 AA8_242X_GPIO58,
471 Y20_24XX_GPIO60,
472 W4__24XX_GPIO74,
473 M15_24XX_GPIO92,
474 V14_24XX_GPIO117,
475
476 /* 242x DBG GPIO */
477 V4_242X_GPIO49,
478 W2_242X_GPIO50,
479 U4_242X_GPIO51,
480 V3_242X_GPIO52,
481 V2_242X_GPIO53,
482 V6_242X_GPIO53,
483 T4_242X_GPIO54,
484 Y4_242X_GPIO54,
485 T3_242X_GPIO55,
486 U2_242X_GPIO56,
487
488 /* 24xx external DMA requests */
489 AA10_242X_DMAREQ0,
490 AA6_242X_DMAREQ1,
491 E4_242X_DMAREQ2,
492 G4_242X_DMAREQ3,
493 D3_242X_DMAREQ4,
494 E3_242X_DMAREQ5,
495
496 P20_24XX_TSC_IRQ,
497
498 /* UART3 */
499 K15_24XX_UART3_TX,
500 K14_24XX_UART3_RX,
501
502 /* MMC/SDIO */
503 G19_24XX_MMC_CLKO,
504 H18_24XX_MMC_CMD,
505 F20_24XX_MMC_DAT0,
506 H14_24XX_MMC_DAT1,
507 E19_24XX_MMC_DAT2,
508 D19_24XX_MMC_DAT3,
509 F19_24XX_MMC_DAT_DIR0,
510 E20_24XX_MMC_DAT_DIR1,
511 F18_24XX_MMC_DAT_DIR2,
512 E18_24XX_MMC_DAT_DIR3,
513 G18_24XX_MMC_CMD_DIR,
514 H15_24XX_MMC_CLKI,
515
516 /* Keypad GPIO*/
517 T19_24XX_KBR0,
518 R19_24XX_KBR1,
519 V18_24XX_KBR2,
520 M21_24XX_KBR3,
521 E5__24XX_KBR4,
522 M18_24XX_KBR5,
523 R20_24XX_KBC0,
524 M14_24XX_KBC1,
525 H19_24XX_KBC2,
526 V17_24XX_KBC3,
527 P21_24XX_KBC4,
528 L14_24XX_KBC5,
529 N19_24XX_KBC6,
530
531 /* 24xx Menelaus Keypad GPIO */
532 B3__24XX_KBR5,
533 AA4_24XX_KBC2,
534 B13_24XX_KBC6,
535 };
536
537 #ifdef CONFIG_OMAP_MUX
538 /* setup pin muxing in Linux */
539 extern int omap1_mux_init(void);
540 extern int omap2_mux_init(void);
541 extern int omap_mux_register(struct pin_config * pins, unsigned long size);
542 extern int omap_cfg_reg(unsigned long reg_cfg);
543 extern int omap_cfg_probe(unsigned long reg_cfg);
544 #else
545 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
omap1_mux_init(void)546 static inline int omap1_mux_init(void) { return 0; }
omap2_mux_init(void)547 static inline int omap2_mux_init(void) { return 0; }
omap_cfg_reg(unsigned long reg_cfg)548 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
omap_cfg_probe(unsigned long reg_cfg)549 static inline int omap_cfg_probe(unsigned long reg_cfg) { return 0; }
550 #endif
551
552 #endif
553