1This file is a partial list of people who have contributed to the LLVM 2project. If you have contributed a patch or made some other contribution to 3LLVM, please submit a patch to this file to add yourself, and it will be 4done! 5 6The list is sorted by surname and formatted to allow easy grepping and 7beautification by scripts. The fields are: name (N), email (E), web-address 8(W), PGP key ID and fingerprint (P), description (D), snail-mail address 9(S), and (I) IRC handle. 10 11 12N: Vikram Adve 13E: vadve@cs.uiuc.edu 14W: http://www.cs.uiuc.edu/~vadve/ 15D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM 16 17N: Owen Anderson 18E: resistor@mac.com 19D: LCSSA pass and related LoopUnswitch work 20D: GVNPRE pass, DataLayout refactoring, random improvements 21 22N: Henrik Bach 23D: MingW Win32 API portability layer 24 25N: Aaron Ballman 26E: aaron@aaronballman.com 27D: __declspec attributes, Windows support, general bug fixing 28 29N: Nate Begeman 30E: natebegeman@mac.com 31D: PowerPC backend developer 32D: Target-independent code generator and analysis improvements 33 34N: Daniel Berlin 35E: dberlin@dberlin.org 36D: ET-Forest implementation. 37D: Sparse bitmap 38 39N: David Blaikie 40E: dblaikie@gmail.com 41D: General bug fixing/fit & finish, mostly in Clang 42 43N: Neil Booth 44E: neil@daikokuya.co.uk 45D: APFloat implementation. 46 47N: Misha Brukman 48E: brukman+llvm@uiuc.edu 49W: http://misha.brukman.net 50D: Portions of X86 and Sparc JIT compilers, PowerPC backend 51D: Incremental bitcode loader 52 53N: Cameron Buschardt 54E: buschard@uiuc.edu 55D: The `mem2reg' pass - promotes values stored in memory to registers 56 57N: Brendon Cahoon 58E: bcahoon@codeaurora.org 59D: Loop unrolling with run-time trip counts. 60 61N: Chandler Carruth 62E: chandlerc@gmail.com 63E: chandlerc@google.com 64D: Hashing algorithms and interfaces 65D: Inline cost analysis 66D: Machine block placement pass 67D: SROA 68 69N: Casey Carter 70E: ccarter@uiuc.edu 71D: Fixes to the Reassociation pass, various improvement patches 72 73N: Evan Cheng 74E: evan.cheng@apple.com 75D: ARM and X86 backends 76D: Instruction scheduler improvements 77D: Register allocator improvements 78D: Loop optimizer improvements 79D: Target-independent code generator improvements 80 81N: Dan Villiom Podlaski Christiansen 82E: danchr@gmail.com 83E: danchr@cs.au.dk 84W: http://villiom.dk 85D: LLVM Makefile improvements 86D: Clang diagnostic & driver tweaks 87S: Aarhus, Denmark 88 89N: Jeff Cohen 90E: jeffc@jolt-lang.org 91W: http://jolt-lang.org 92D: Native Win32 API portability layer 93 94N: John T. Criswell 95E: criswell@uiuc.edu 96D: Original Autoconf support, documentation improvements, bug fixes 97 98N: Anshuman Dasgupta 99E: adasgupt@codeaurora.org 100D: Deterministic finite automaton based infrastructure for VLIW packetization 101 102N: Stefanus Du Toit 103E: stefanus.du.toit@intel.com 104D: Bug fixes and minor improvements 105 106N: Rafael Avila de Espindola 107E: rafael.espindola@gmail.com 108D: The ARM backend 109 110N: Alkis Evlogimenos 111E: alkis@evlogimenos.com 112D: Linear scan register allocator, many codegen improvements, Java frontend 113 114N: Hal Finkel 115E: hfinkel@anl.gov 116D: Basic-block autovectorization, PowerPC backend improvements 117 118N: Ryan Flynn 119E: pizza@parseerror.com 120D: Miscellaneous bug fixes 121 122N: Brian Gaeke 123E: gaeke@uiuc.edu 124W: http://www.students.uiuc.edu/~gaeke/ 125D: Portions of X86 static and JIT compilers; initial SparcV8 backend 126D: Dynamic trace optimizer 127D: FreeBSD/X86 compatibility fixes, the llvm-nm tool 128 129N: Nicolas Geoffray 130E: nicolas.geoffray@lip6.fr 131W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/ 132D: PPC backend fixes for Linux 133 134N: Louis Gerbarg 135D: Portions of the PowerPC backend 136 137N: Saem Ghani 138E: saemghani@gmail.com 139D: Callgraph class cleanups 140 141N: Mikhail Glushenkov 142E: foldr@codedgers.com 143D: Author of llvmc2 144 145N: Dan Gohman 146E: dan433584@gmail.com 147D: Miscellaneous bug fixes 148 149N: David Goodwin 150E: david@goodwinz.net 151D: Thumb-2 code generator 152 153N: David Greene 154E: greened@obbligato.org 155D: Miscellaneous bug fixes 156D: Register allocation refactoring 157 158N: Gabor Greif 159E: ggreif@gmail.com 160D: Improvements for space efficiency 161 162N: James Grosbach 163E: grosbach@apple.com 164D: SjLj exception handling support 165D: General fixes and improvements for the ARM back-end 166D: MCJIT 167D: ARM integrated assembler and assembly parser 168 169N: Lang Hames 170E: lhames@gmail.com 171D: PBQP-based register allocator 172 173N: Gordon Henriksen 174E: gordonhenriksen@mac.com 175D: Pluggable GC support 176D: C interface 177D: Ocaml bindings 178 179N: Raul Fernandes Herbster 180E: raul@dsc.ufcg.edu.br 181D: JIT support for ARM 182 183N: Paolo Invernizzi 184E: arathorn@fastwebnet.it 185D: Visual C++ compatibility fixes 186 187N: Patrick Jenkins 188E: patjenk@wam.umd.edu 189D: Nightly Tester 190 191N: Dale Johannesen 192E: dalej@apple.com 193D: ARM constant islands improvements 194D: Tail merging improvements 195D: Rewrite X87 back end 196D: Use APFloat for floating point constants widely throughout compiler 197D: Implement X87 long double 198 199N: Brad Jones 200E: kungfoomaster@nondot.org 201D: Support for packed types 202 203N: Rod Kay 204E: rkay@auroraux.org 205D: Author of LLVM Ada bindings 206 207N: Eric Kidd 208W: http://randomhacks.net/ 209D: llvm-config script 210 211N: Anton Korobeynikov 212E: asl@math.spbu.ru 213D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv. 214D: x86/linux PIC codegen, aliases, regparm/visibility attributes 215D: Switch lowering refactoring 216 217N: Sumant Kowshik 218E: kowshik@uiuc.edu 219D: Author of the original C backend 220 221N: Benjamin Kramer 222E: benny.kra@gmail.com 223D: Miscellaneous bug fixes 224 225N: Sundeep Kushwaha 226E: sundeepk@codeaurora.org 227D: Implemented DFA-based target independent VLIW packetizer 228 229N: Christopher Lamb 230E: christopher.lamb@gmail.com 231D: aligned load/store support, parts of noalias and restrict support 232D: vreg subreg infrastructure, X86 codegen improvements based on subregs 233D: address spaces 234 235N: Jim Laskey 236E: jlaskey@apple.com 237D: Improvements to the PPC backend, instruction scheduling 238D: Debug and Dwarf implementation 239D: Auto upgrade mangler 240D: llvm-gcc4 svn wrangler 241 242N: Chris Lattner 243E: sabre@nondot.org 244W: http://nondot.org/~sabre/ 245D: Primary architect of LLVM 246 247N: Tanya Lattner (Tanya Brethour) 248E: tonic@nondot.org 249W: http://nondot.org/~tonic/ 250D: The initial llvm-ar tool, converted regression testsuite to dejagnu 251D: Modulo scheduling in the SparcV9 backend 252D: Release manager (1.7+) 253 254N: Sylvestre Ledru 255E: sylvestre@debian.org 256W: http://sylvesre.ledru.info/ 257D: Debian and Ubuntu packaging 258D: Continous integration with jenkins 259 260N: Andrew Lenharth 261E: alenhar2@cs.uiuc.edu 262W: http://www.lenharth.org/~andrewl/ 263D: Alpha backend 264D: Sampling based profiling 265 266N: Nick Lewycky 267E: nicholas@mxc.ca 268D: PredicateSimplifier pass 269 270N: Tony Linthicum, et. al. 271E: tlinth@codeaurora.org 272D: Backend for Qualcomm's Hexagon VLIW processor. 273 274N: Bruno Cardoso Lopes 275E: bruno.cardoso@gmail.com 276W: http://www.brunocardoso.org 277D: The Mips backend 278 279N: Duraid Madina 280E: duraid@octopus.com.au 281W: http://kinoko.c.u-tokyo.ac.jp/~duraid/ 282D: IA64 backend, BigBlock register allocator 283 284N: John McCall 285E: rjmccall@apple.com 286D: Clang semantic analysis and IR generation 287 288N: Michael McCracken 289E: michael.mccracken@gmail.com 290D: Line number support for llvmgcc 291 292N: Vladimir Merzliakov 293E: wanderer@rsu.ru 294D: Test suite fixes for FreeBSD 295 296N: Scott Michel 297E: scottm@aero.org 298D: Added STI Cell SPU backend. 299 300N: Kai Nacke 301E: kai@redstar.de 302D: Support for implicit TLS model used with MS VC runtime 303D: Dumping of Win64 EH structures 304 305N: Takumi Nakamura 306E: geek4civic@gmail.com 307E: chapuni@hf.rim.or.jp 308D: Cygwin and MinGW support. 309D: Win32 tweaks. 310S: Yokohama, Japan 311 312N: Edward O'Callaghan 313E: eocallaghan@auroraux.org 314W: http://www.auroraux.org 315D: Add Clang support with various other improvements to utils/NewNightlyTest.pl 316D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings 317D: and error clean ups. 318 319N: Morten Ofstad 320E: morten@hue.no 321D: Visual C++ compatibility fixes 322 323N: Jakob Stoklund Olesen 324E: stoklund@2pi.dk 325D: Machine code verifier 326D: Blackfin backend 327D: Fast register allocator 328D: Greedy register allocator 329 330N: Richard Osborne 331E: richard@xmos.com 332D: XCore backend 333 334N: Devang Patel 335E: dpatel@apple.com 336D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate 337D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements 338D: Optimizer improvements, Loop Index Split 339 340N: Wesley Peck 341E: peckw@wesleypeck.com 342W: http://wesleypeck.com/ 343D: MicroBlaze backend 344 345N: Francois Pichet 346E: pichet2000@gmail.com 347D: MSVC support 348 349N: Vladimir Prus 350W: http://vladimir_prus.blogspot.com 351E: ghost@cs.msu.su 352D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass 353 354N: Kalle Raiskila 355E: kalle.rasikila@nokia.com 356D: Some bugfixes to CellSPU 357 358N: Xerxes Ranby 359E: xerxes@zafena.se 360D: Cmake dependency chain and various bug fixes 361 362N: Alex Rosenberg 363E: alexr@leftfield.org 364I: arosenberg 365D: ARM calling conventions rewrite, hard float support 366 367N: Chad Rosier 368E: mcrosier@apple.com 369D: ARM fast-isel improvements 370D: Performance monitoring 371 372N: Nadav Rotem 373E: nrotem@apple.com 374D: X86 code generation improvements, Loop Vectorizer. 375 376N: Roman Samoilov 377E: roman@codedgers.com 378D: MSIL backend 379 380N: Duncan Sands 381E: baldrick@free.fr 382I: baldrick 383D: Ada support in llvm-gcc 384D: Dragonegg plugin 385D: Exception handling improvements 386D: Type legalizer rewrite 387 388N: Ruchira Sasanka 389E: sasanka@uiuc.edu 390D: Graph coloring register allocator for the Sparc64 backend 391 392N: Arnold Schwaighofer 393E: arnold.schwaighofer@gmail.com 394D: Tail call optimization for the x86 backend 395 396N: Shantonu Sen 397E: ssen@apple.com 398D: Miscellaneous bug fixes 399 400N: Anand Shukla 401E: ashukla@cs.uiuc.edu 402D: The `paths' pass 403 404N: Michael J. Spencer 405E: bigcheesegs@gmail.com 406D: Shepherding Windows COFF support into MC. 407D: Lots of Windows stuff. 408 409N: Reid Spencer 410E: rspencer@reidspencer.com 411W: http://reidspencer.com/ 412D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid 413 414N: Craig Topper 415E: craig.topper@gmail.com 416D: X86 codegen and disassembler improvements. AVX2 support. 417 418N: Edwin Torok 419E: edwintorok@gmail.com 420D: Miscellaneous bug fixes 421 422N: Adam Treat 423E: manyoso@yahoo.com 424D: C++ bugs filed, and C++ front-end bug fixes. 425 426N: Lauro Ramos Venancio 427E: lauro.venancio@indt.org.br 428D: ARM backend improvements 429D: Thread Local Storage implementation 430 431N: Bill Wendling 432I: wendling 433E: wendling@apple.com 434D: Release manager 435D: Bunches of stuff 436 437N: Bob Wilson 438E: bob.wilson@acm.org 439D: Advanced SIMD (NEON) support in the ARM backend 440