1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the Hexagon target. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Target-independent interfaces which we are implementing 16//===----------------------------------------------------------------------===// 17 18include "llvm/Target/Target.td" 19 20//===----------------------------------------------------------------------===// 21// Hexagon Subtarget features. 22//===----------------------------------------------------------------------===// 23 24// Hexagon Archtectures 25def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2", 26 "Hexagon v2">; 27def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3", 28 "Hexagon v3">; 29def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4", 30 "Hexagon v4">; 31def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5", 32 "Hexagon v5">; 33 34//===----------------------------------------------------------------------===// 35// Hexagon Instruction Predicate Definitions. 36//===----------------------------------------------------------------------===// 37def HasV2T : Predicate<"Subtarget.hasV2TOps()">; 38def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">; 39def NoV2T : Predicate<"!Subtarget.hasV2TOps()">; 40def HasV3T : Predicate<"Subtarget.hasV3TOps()">; 41def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">; 42def NoV3T : Predicate<"!Subtarget.hasV3TOps()">; 43def HasV4T : Predicate<"Subtarget.hasV4TOps()">; 44def NoV4T : Predicate<"!Subtarget.hasV4TOps()">; 45def HasV5T : Predicate<"Subtarget.hasV5TOps()">; 46def NoV5T : Predicate<"!Subtarget.hasV5TOps()">; 47def UseMEMOP : Predicate<"Subtarget.useMemOps()">; 48def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">; 49 50//===----------------------------------------------------------------------===// 51// Classes used for relation maps. 52//===----------------------------------------------------------------------===// 53// PredRel - Filter class used to relate non-predicated instructions with their 54// predicated forms. 55class PredRel; 56// PredNewRel - Filter class used to relate predicated instructions with their 57// predicate-new forms. 58class PredNewRel: PredRel; 59// ImmRegRel - Filter class used to relate instructions having reg-reg form 60// with their reg-imm counterparts. 61class ImmRegRel; 62// NewValueRel - Filter class used to relate regular store instructions with 63// their new-value store form. 64class NewValueRel: PredNewRel; 65// NewValueRel - Filter class used to relate load/store instructions having 66// different addressing modes with each other. 67class AddrModeRel: NewValueRel; 68 69//===----------------------------------------------------------------------===// 70// Generate mapping table to relate non-predicate instructions with their 71// predicated formats - true and false. 72// 73 74def getPredOpcode : InstrMapping { 75 let FilterClass = "PredRel"; 76 // Instructions with the same BaseOpcode and isNVStore values form a row. 77 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"]; 78 // Instructions with the same predicate sense form a column. 79 let ColFields = ["PredSense"]; 80 // The key column is the unpredicated instructions. 81 let KeyCol = [""]; 82 // Value columns are PredSense=true and PredSense=false 83 let ValueCols = [["true"], ["false"]]; 84} 85 86//===----------------------------------------------------------------------===// 87// Generate mapping table to relate predicate-true instructions with their 88// predicate-false forms 89// 90def getFalsePredOpcode : InstrMapping { 91 let FilterClass = "PredRel"; 92 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"]; 93 let ColFields = ["PredSense"]; 94 let KeyCol = ["true"]; 95 let ValueCols = [["false"]]; 96} 97 98//===----------------------------------------------------------------------===// 99// Generate mapping table to relate predicate-false instructions with their 100// predicate-true forms 101// 102def getTruePredOpcode : InstrMapping { 103 let FilterClass = "PredRel"; 104 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"]; 105 let ColFields = ["PredSense"]; 106 let KeyCol = ["false"]; 107 let ValueCols = [["true"]]; 108} 109 110//===----------------------------------------------------------------------===// 111// Generate mapping table to relate predicated instructions with their .new 112// format. 113// 114def getPredNewOpcode : InstrMapping { 115 let FilterClass = "PredNewRel"; 116 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 117 let ColFields = ["PNewValue"]; 118 let KeyCol = [""]; 119 let ValueCols = [["new"]]; 120} 121 122//===----------------------------------------------------------------------===// 123// Generate mapping table to relate .new predicated instructions with their old 124// format. 125// 126def getPredOldOpcode : InstrMapping { 127 let FilterClass = "PredNewRel"; 128 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; 129 let ColFields = ["PNewValue"]; 130 let KeyCol = ["new"]; 131 let ValueCols = [[""]]; 132} 133 134//===----------------------------------------------------------------------===// 135// Generate mapping table to relate store instructions with their new-value 136// format. 137// 138def getNewValueOpcode : InstrMapping { 139 let FilterClass = "NewValueRel"; 140 let RowFields = ["BaseOpcode", "PredSense", "PNewValue"]; 141 let ColFields = ["NValueST"]; 142 let KeyCol = ["false"]; 143 let ValueCols = [["true"]]; 144} 145 146//===----------------------------------------------------------------------===// 147// Generate mapping table to relate new-value store instructions with their old 148// format. 149// 150def getNonNVStore : InstrMapping { 151 let FilterClass = "NewValueRel"; 152 let RowFields = ["BaseOpcode", "PredSense", "PNewValue"]; 153 let ColFields = ["NValueST"]; 154 let KeyCol = ["true"]; 155 let ValueCols = [["false"]]; 156} 157 158def getBasedWithImmOffset : InstrMapping { 159 let FilterClass = "AddrModeRel"; 160 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 161 "isMEMri", "isFloat"]; 162 let ColFields = ["addrMode"]; 163 let KeyCol = ["Absolute"]; 164 let ValueCols = [["BaseImmOffset"]]; 165} 166 167def getBaseWithRegOffset : InstrMapping { 168 let FilterClass = "AddrModeRel"; 169 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 170 let ColFields = ["addrMode"]; 171 let KeyCol = ["BaseImmOffset"]; 172 let ValueCols = [["BaseRegOffset"]]; 173} 174 175def getRegForm : InstrMapping { 176 let FilterClass = "ImmRegRel"; 177 let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; 178 let ColFields = ["InputType"]; 179 let KeyCol = ["imm"]; 180 let ValueCols = [["reg"]]; 181} 182 183//===----------------------------------------------------------------------===// 184// Register File, Calling Conv, Instruction Descriptions 185//===----------------------------------------------------------------------===// 186include "HexagonSchedule.td" 187include "HexagonRegisterInfo.td" 188include "HexagonCallingConv.td" 189include "HexagonInstrInfo.td" 190include "HexagonIntrinsics.td" 191include "HexagonIntrinsicsDerived.td" 192 193def HexagonInstrInfo : InstrInfo; 194 195//===----------------------------------------------------------------------===// 196// Hexagon processors supported. 197//===----------------------------------------------------------------------===// 198 199class Proc<string Name, SchedMachineModel Model, 200 list<SubtargetFeature> Features> 201 : ProcessorModel<Name, Model, Features>; 202 203def : Proc<"hexagonv2", HexagonModel, [ArchV2]>; 204def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>; 205def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>; 206def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; 207 208 209// Hexagon Uses the MC printer for assembler output, so make sure the TableGen 210// AsmWriter bits get associated with the correct class. 211def HexagonAsmWriter : AsmWriter { 212 string AsmWriterClassName = "InstPrinter"; 213 bit isMCAsmWriter = 1; 214} 215 216//===----------------------------------------------------------------------===// 217// Declare the target which we are implementing 218//===----------------------------------------------------------------------===// 219 220def Hexagon : Target { 221 // Pull in Instruction Info: 222 let InstructionSet = HexagonInstrInfo; 223 224 let AssemblyWriters = [HexagonAsmWriter]; 225} 226