1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14
15 #include "MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "llvm/MC/MCAsmBackend.h"
18 #include "llvm/MC/MCAssembler.h"
19 #include "llvm/MC/MCDirectives.h"
20 #include "llvm/MC/MCELFObjectWriter.h"
21 #include "llvm/MC/MCFixupKindInfo.h"
22 #include "llvm/MC/MCObjectWriter.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26
27 using namespace llvm;
28
29 // Prepare value for the target space for it
adjustFixupValue(unsigned Kind,uint64_t Value)30 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
31
32 // Add/subtract and shift
33 switch (Kind) {
34 default:
35 return 0;
36 case FK_GPRel_4:
37 case FK_Data_4:
38 case FK_Data_8:
39 case Mips::fixup_Mips_LO16:
40 case Mips::fixup_Mips_GPREL16:
41 case Mips::fixup_Mips_GPOFF_HI:
42 case Mips::fixup_Mips_GPOFF_LO:
43 case Mips::fixup_Mips_GOT_PAGE:
44 case Mips::fixup_Mips_GOT_OFST:
45 case Mips::fixup_Mips_GOT_DISP:
46 case Mips::fixup_Mips_GOT_LO16:
47 case Mips::fixup_Mips_CALL_LO16:
48 break;
49 case Mips::fixup_Mips_PC16:
50 // So far we are only using this type for branches.
51 // For branches we start 1 instruction after the branch
52 // so the displacement will be one instruction size less.
53 Value -= 4;
54 // The displacement is then divided by 4 to give us an 18 bit
55 // address range.
56 Value >>= 2;
57 break;
58 case Mips::fixup_Mips_26:
59 // So far we are only using this type for jumps.
60 // The displacement is then divided by 4 to give us an 28 bit
61 // address range.
62 Value >>= 2;
63 break;
64 case Mips::fixup_Mips_HI16:
65 case Mips::fixup_Mips_GOT_Local:
66 case Mips::fixup_Mips_GOT_HI16:
67 case Mips::fixup_Mips_CALL_HI16:
68 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
69 Value = ((Value + 0x8000) >> 16) & 0xffff;
70 break;
71 case Mips::fixup_Mips_HIGHER:
72 // Get the 3rd 16-bits.
73 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
74 break;
75 case Mips::fixup_Mips_HIGHEST:
76 // Get the 4th 16-bits.
77 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
78 break;
79 }
80
81 return Value;
82 }
83
84 namespace {
85 class MipsAsmBackend : public MCAsmBackend {
86 Triple::OSType OSType;
87 bool IsLittle; // Big or little endian
88 bool Is64Bit; // 32 or 64 bit words
89
90 public:
MipsAsmBackend(const Target & T,Triple::OSType _OSType,bool _isLittle,bool _is64Bit)91 MipsAsmBackend(const Target &T, Triple::OSType _OSType,
92 bool _isLittle, bool _is64Bit)
93 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
94
createObjectWriter(raw_ostream & OS) const95 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
96 return createMipsELFObjectWriter(OS,
97 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
98 }
99
100 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
101 /// data fragment, at the offset specified by the fixup and following the
102 /// fixup kind as appropriate.
applyFixup(const MCFixup & Fixup,char * Data,unsigned DataSize,uint64_t Value) const103 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
104 uint64_t Value) const {
105 MCFixupKind Kind = Fixup.getKind();
106 Value = adjustFixupValue((unsigned)Kind, Value);
107
108 if (!Value)
109 return; // Doesn't change encoding.
110
111 // Where do we start in the object
112 unsigned Offset = Fixup.getOffset();
113 // Number of bytes we need to fixup
114 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
115 // Used to point to big endian bytes
116 unsigned FullSize;
117
118 switch ((unsigned)Kind) {
119 case Mips::fixup_Mips_16:
120 FullSize = 2;
121 break;
122 case Mips::fixup_Mips_64:
123 FullSize = 8;
124 break;
125 default:
126 FullSize = 4;
127 break;
128 }
129
130 // Grab current value, if any, from bits.
131 uint64_t CurVal = 0;
132
133 for (unsigned i = 0; i != NumBytes; ++i) {
134 unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
135 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
136 }
137
138 uint64_t Mask = ((uint64_t)(-1) >>
139 (64 - getFixupKindInfo(Kind).TargetSize));
140 CurVal |= Value & Mask;
141
142 // Write out the fixed up bytes back to the code/data bits.
143 for (unsigned i = 0; i != NumBytes; ++i) {
144 unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
145 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
146 }
147 }
148
getNumFixupKinds() const149 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
150
getFixupKindInfo(MCFixupKind Kind) const151 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
152 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
153 // This table *must* be in same the order of fixup_* kinds in
154 // MipsFixupKinds.h.
155 //
156 // name offset bits flags
157 { "fixup_Mips_16", 0, 16, 0 },
158 { "fixup_Mips_32", 0, 32, 0 },
159 { "fixup_Mips_REL32", 0, 32, 0 },
160 { "fixup_Mips_26", 0, 26, 0 },
161 { "fixup_Mips_HI16", 0, 16, 0 },
162 { "fixup_Mips_LO16", 0, 16, 0 },
163 { "fixup_Mips_GPREL16", 0, 16, 0 },
164 { "fixup_Mips_LITERAL", 0, 16, 0 },
165 { "fixup_Mips_GOT_Global", 0, 16, 0 },
166 { "fixup_Mips_GOT_Local", 0, 16, 0 },
167 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
168 { "fixup_Mips_CALL16", 0, 16, 0 },
169 { "fixup_Mips_GPREL32", 0, 32, 0 },
170 { "fixup_Mips_SHIFT5", 6, 5, 0 },
171 { "fixup_Mips_SHIFT6", 6, 5, 0 },
172 { "fixup_Mips_64", 0, 64, 0 },
173 { "fixup_Mips_TLSGD", 0, 16, 0 },
174 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
175 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
176 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
177 { "fixup_Mips_TLSLDM", 0, 16, 0 },
178 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
179 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
180 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
181 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
182 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
183 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
184 { "fixup_Mips_GOT_OFST", 0, 16, 0 },
185 { "fixup_Mips_GOT_DISP", 0, 16, 0 },
186 { "fixup_Mips_HIGHER", 0, 16, 0 },
187 { "fixup_Mips_HIGHEST", 0, 16, 0 },
188 { "fixup_Mips_GOT_HI16", 0, 16, 0 },
189 { "fixup_Mips_GOT_LO16", 0, 16, 0 },
190 { "fixup_Mips_CALL_HI16", 0, 16, 0 },
191 { "fixup_Mips_CALL_LO16", 0, 16, 0 }
192 };
193
194 if (Kind < FirstTargetFixupKind)
195 return MCAsmBackend::getFixupKindInfo(Kind);
196
197 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
198 "Invalid kind!");
199 return Infos[Kind - FirstTargetFixupKind];
200 }
201
202 /// @name Target Relaxation Interfaces
203 /// @{
204
205 /// MayNeedRelaxation - Check whether the given instruction may need
206 /// relaxation.
207 ///
208 /// \param Inst - The instruction to test.
mayNeedRelaxation(const MCInst & Inst) const209 bool mayNeedRelaxation(const MCInst &Inst) const {
210 return false;
211 }
212
213 /// fixupNeedsRelaxation - Target specific predicate for whether a given
214 /// fixup requires the associated instruction to be relaxed.
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const215 bool fixupNeedsRelaxation(const MCFixup &Fixup,
216 uint64_t Value,
217 const MCRelaxableFragment *DF,
218 const MCAsmLayout &Layout) const {
219 // FIXME.
220 assert(0 && "RelaxInstruction() unimplemented");
221 return false;
222 }
223
224 /// RelaxInstruction - Relax the instruction in the given fragment
225 /// to the next wider instruction.
226 ///
227 /// \param Inst - The instruction to relax, which may be the same
228 /// as the output.
229 /// \param [out] Res On return, the relaxed instruction.
relaxInstruction(const MCInst & Inst,MCInst & Res) const230 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
231 }
232
233 /// @}
234
235 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
236 /// to the given output. If the target cannot generate such a sequence,
237 /// it should return an error.
238 ///
239 /// \return - True on success.
writeNopData(uint64_t Count,MCObjectWriter * OW) const240 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
241 // Check for a less than instruction size number of bytes
242 // FIXME: 16 bit instructions are not handled yet here.
243 // We shouldn't be using a hard coded number for instruction size.
244 if (Count % 4) return false;
245
246 uint64_t NumNops = Count / 4;
247 for (uint64_t i = 0; i != NumNops; ++i)
248 OW->Write32(0);
249 return true;
250 }
251 }; // class MipsAsmBackend
252
253 } // namespace
254
255 // MCAsmBackend
createMipsAsmBackendEL32(const Target & T,StringRef TT,StringRef CPU)256 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT,
257 StringRef CPU) {
258 return new MipsAsmBackend(T, Triple(TT).getOS(),
259 /*IsLittle*/true, /*Is64Bit*/false);
260 }
261
createMipsAsmBackendEB32(const Target & T,StringRef TT,StringRef CPU)262 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT,
263 StringRef CPU) {
264 return new MipsAsmBackend(T, Triple(TT).getOS(),
265 /*IsLittle*/false, /*Is64Bit*/false);
266 }
267
createMipsAsmBackendEL64(const Target & T,StringRef TT,StringRef CPU)268 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT,
269 StringRef CPU) {
270 return new MipsAsmBackend(T, Triple(TT).getOS(),
271 /*IsLittle*/true, /*Is64Bit*/true);
272 }
273
createMipsAsmBackendEB64(const Target & T,StringRef TT,StringRef CPU)274 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT,
275 StringRef CPU) {
276 return new MipsAsmBackend(T, Triple(TT).getOS(),
277 /*IsLittle*/false, /*Is64Bit*/true);
278 }
279
280