1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SystemZMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/SystemZMCTargetDesc.h"
16 #include "MCTargetDesc/SystemZMCFixups.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInstrInfo.h"
21
22 using namespace llvm;
23
24 namespace {
25 class SystemZMCCodeEmitter : public MCCodeEmitter {
26 const MCInstrInfo &MCII;
27 MCContext &Ctx;
28
29 public:
SystemZMCCodeEmitter(const MCInstrInfo & mcii,MCContext & ctx)30 SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
31 : MCII(mcii), Ctx(ctx) {
32 }
33
~SystemZMCCodeEmitter()34 ~SystemZMCCodeEmitter() {}
35
36 // OVerride MCCodeEmitter.
37 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
38 SmallVectorImpl<MCFixup> &Fixups) const
39 LLVM_OVERRIDE;
40
41 private:
42 // Automatically generated by TableGen.
43 uint64_t getBinaryCodeForInstr(const MCInst &MI,
44 SmallVectorImpl<MCFixup> &Fixups) const;
45
46 // Called by the TableGen code to get the binary encoding of operand
47 // MO in MI. Fixups is the list of fixups against MI.
48 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
49 SmallVectorImpl<MCFixup> &Fixups) const;
50
51 // Called by the TableGen code to get the binary encoding of an address.
52 // The index or length, if any, is encoded first, followed by the base,
53 // followed by the displacement. In a 20-bit displacement,
54 // the low 12 bits are encoded before the high 8 bits.
55 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
56 SmallVectorImpl<MCFixup> &Fixups) const;
57 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
58 SmallVectorImpl<MCFixup> &Fixups) const;
59 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
60 SmallVectorImpl<MCFixup> &Fixups) const;
61 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
62 SmallVectorImpl<MCFixup> &Fixups) const;
63 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
64 SmallVectorImpl<MCFixup> &Fixups) const;
65
66 // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
67 // Offset bytes from the start of MI. Add the fixup to Fixups
68 // and return the in-place addend, which since we're a RELA target
69 // is always 0.
70 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
71 SmallVectorImpl<MCFixup> &Fixups,
72 unsigned Kind, int64_t Offset) const;
73
getPC16DBLEncoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const74 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
75 SmallVectorImpl<MCFixup> &Fixups) const {
76 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2);
77 }
getPC32DBLEncoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const78 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
79 SmallVectorImpl<MCFixup> &Fixups) const {
80 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2);
81 }
getPLT16DBLEncoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const82 uint64_t getPLT16DBLEncoding(const MCInst &MI, unsigned OpNum,
83 SmallVectorImpl<MCFixup> &Fixups) const {
84 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PLT16DBL, 2);
85 }
getPLT32DBLEncoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const86 uint64_t getPLT32DBLEncoding(const MCInst &MI, unsigned OpNum,
87 SmallVectorImpl<MCFixup> &Fixups) const {
88 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PLT32DBL, 2);
89 }
90 };
91 }
92
createSystemZMCCodeEmitter(const MCInstrInfo & MCII,const MCRegisterInfo & MRI,const MCSubtargetInfo & MCSTI,MCContext & Ctx)93 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
94 const MCRegisterInfo &MRI,
95 const MCSubtargetInfo &MCSTI,
96 MCContext &Ctx) {
97 return new SystemZMCCodeEmitter(MCII, Ctx);
98 }
99
100 void SystemZMCCodeEmitter::
EncodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups) const101 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
102 SmallVectorImpl<MCFixup> &Fixups) const {
103 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
104 unsigned Size = MCII.get(MI.getOpcode()).getSize();
105 // Big-endian insertion of Size bytes.
106 unsigned ShiftValue = (Size * 8) - 8;
107 for (unsigned I = 0; I != Size; ++I) {
108 OS << uint8_t(Bits >> ShiftValue);
109 ShiftValue -= 8;
110 }
111 }
112
113 uint64_t SystemZMCCodeEmitter::
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups) const114 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
115 SmallVectorImpl<MCFixup> &Fixups) const {
116 if (MO.isReg())
117 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
118 if (MO.isImm())
119 return static_cast<uint64_t>(MO.getImm());
120 llvm_unreachable("Unexpected operand type!");
121 }
122
123 uint64_t SystemZMCCodeEmitter::
getBDAddr12Encoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const124 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
125 SmallVectorImpl<MCFixup> &Fixups) const {
126 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
127 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
128 assert(isUInt<4>(Base) && isUInt<12>(Disp));
129 return (Base << 12) | Disp;
130 }
131
132 uint64_t SystemZMCCodeEmitter::
getBDAddr20Encoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const133 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
134 SmallVectorImpl<MCFixup> &Fixups) const {
135 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
136 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
137 assert(isUInt<4>(Base) && isInt<20>(Disp));
138 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
139 }
140
141 uint64_t SystemZMCCodeEmitter::
getBDXAddr12Encoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const142 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
143 SmallVectorImpl<MCFixup> &Fixups) const {
144 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
145 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
146 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
147 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
148 return (Index << 16) | (Base << 12) | Disp;
149 }
150
151 uint64_t SystemZMCCodeEmitter::
getBDXAddr20Encoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const152 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
153 SmallVectorImpl<MCFixup> &Fixups) const {
154 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
155 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
156 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
157 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
158 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
159 | ((Disp & 0xff000) >> 12);
160 }
161
162 uint64_t SystemZMCCodeEmitter::
getBDLAddr12Len8Encoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups) const163 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
164 SmallVectorImpl<MCFixup> &Fixups) const {
165 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
166 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
167 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1;
168 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
169 return (Len << 16) | (Base << 12) | Disp;
170 }
171
172 uint64_t
getPCRelEncoding(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,unsigned Kind,int64_t Offset) const173 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
174 SmallVectorImpl<MCFixup> &Fixups,
175 unsigned Kind, int64_t Offset) const {
176 const MCOperand &MO = MI.getOperand(OpNum);
177 const MCExpr *Expr;
178 if (MO.isImm())
179 Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx);
180 else {
181 Expr = MO.getExpr();
182 if (Offset) {
183 // The operand value is relative to the start of MI, but the fixup
184 // is relative to the operand field itself, which is Offset bytes
185 // into MI. Add Offset to the relocation value to cancel out
186 // this difference.
187 const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
188 Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
189 }
190 }
191 Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind));
192 return 0;
193 }
194
195 #include "SystemZGenMCCodeEmitter.inc"
196