1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue()); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue()); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), 47 "#ADJCALLSTACKDOWN", 48 [(X86callseq_start timm:$amt)]>, 49 Requires<[In32BitMode]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[In32BitMode]>; 54} 55 56// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 57// a stack adjustment and the codegen must know that they may modify the stack 58// pointer before prolog-epilog rewriting occurs. 59// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 60// sub / add which can clobber EFLAGS. 61let Defs = [RSP, EFLAGS], Uses = [RSP] in { 62def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt), 63 "#ADJCALLSTACKDOWN", 64 [(X86callseq_start timm:$amt)]>, 65 Requires<[In64BitMode]>; 66def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 67 "#ADJCALLSTACKUP", 68 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 69 Requires<[In64BitMode]>; 70} 71 72 73 74// x86-64 va_start lowering magic. 75let usesCustomInserter = 1 in { 76def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 77 (outs), 78 (ins GR8:$al, 79 i64imm:$regsavefi, i64imm:$offset, 80 variable_ops), 81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 82 [(X86vastart_save_xmm_regs GR8:$al, 83 imm:$regsavefi, 84 imm:$offset)]>; 85 86// The VAARG_64 pseudo-instruction takes the address of the va_list, 87// and places the address of the next argument into a register. 88let Defs = [EFLAGS] in 89def VAARG_64 : I<0, Pseudo, 90 (outs GR64:$dst), 91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 92 "#VAARG_64 $dst, $ap, $size, $mode, $align", 93 [(set GR64:$dst, 94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 95 (implicit EFLAGS)]>; 96 97// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 98// targets. These calls are needed to probe the stack when allocating more than 99// 4k bytes in one go. Touching the stack at 4K increments is necessary to 100// ensure that the guard pages used by the OS virtual memory manager are 101// allocated in correct sequence. 102// The main point of having separate instruction are extra unmodelled effects 103// (compared to ordinary calls) like stack pointer change. 104 105let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 107 "# dynamic stack allocation", 108 [(X86WinAlloca)]>; 109 110// When using segmented stacks these are lowered into instructions which first 111// check if the current stacklet has enough free memory. If it does, memory is 112// allocated by bumping the stack pointer. Otherwise memory is allocated from 113// the heap. 114 115let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 116def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 117 "# variable sized alloca for segmented stacks", 118 [(set GR32:$dst, 119 (X86SegAlloca GR32:$size))]>, 120 Requires<[In32BitMode]>; 121 122let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 123def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 124 "# variable sized alloca for segmented stacks", 125 [(set GR64:$dst, 126 (X86SegAlloca GR64:$size))]>, 127 Requires<[In64BitMode]>; 128} 129 130// The MSVC runtime contains an _ftol2 routine for converting floating-point 131// to integer values. It has a strange calling convention: the input is 132// popped from the x87 stack, and the return value is given in EDX:EAX. ECX is 133// used as a temporary register. No other registers (aside from flags) are 134// touched. 135// Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80 136// variant is unnecessary. 137 138let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in { 139 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src), 140 "# win32 fptoui", 141 [(X86WinFTOL RFP32:$src)]>, 142 Requires<[In32BitMode]>; 143 144 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src), 145 "# win32 fptoui", 146 [(X86WinFTOL RFP64:$src)]>, 147 Requires<[In32BitMode]>; 148} 149 150//===----------------------------------------------------------------------===// 151// EH Pseudo Instructions 152// 153let SchedRW = [WriteSystem] in { 154let isTerminator = 1, isReturn = 1, isBarrier = 1, 155 hasCtrlDep = 1, isCodeGenOnly = 1 in { 156def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 157 "ret\t#eh_return, addr: $addr", 158 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 159 160} 161 162let isTerminator = 1, isReturn = 1, isBarrier = 1, 163 hasCtrlDep = 1, isCodeGenOnly = 1 in { 164def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 165 "ret\t#eh_return, addr: $addr", 166 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 167 168} 169 170let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 171 usesCustomInserter = 1 in { 172 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 173 "#EH_SJLJ_SETJMP32", 174 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 175 Requires<[In32BitMode]>; 176 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 177 "#EH_SJLJ_SETJMP64", 178 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 179 Requires<[In64BitMode]>; 180 let isTerminator = 1 in { 181 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 182 "#EH_SJLJ_LONGJMP32", 183 [(X86eh_sjlj_longjmp addr:$buf)]>, 184 Requires<[In32BitMode]>; 185 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 186 "#EH_SJLJ_LONGJMP64", 187 [(X86eh_sjlj_longjmp addr:$buf)]>, 188 Requires<[In64BitMode]>; 189 } 190} 191} // SchedRW 192 193let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 194 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 195 "#EH_SjLj_Setup\t$dst", []>; 196} 197 198//===----------------------------------------------------------------------===// 199// Pseudo instructions used by segmented stacks. 200// 201 202// This is lowered into a RET instruction by MCInstLower. We need 203// this so that we don't have to have a MachineBasicBlock which ends 204// with a RET and also has successors. 205let isPseudo = 1 in { 206def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 207 "", []>; 208 209// This instruction is lowered to a RET followed by a MOV. The two 210// instructions are not generated on a higher level since then the 211// verifier sees a MachineBasicBlock ending with a non-terminator. 212def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 213 "", []>; 214} 215 216//===----------------------------------------------------------------------===// 217// Alias Instructions 218//===----------------------------------------------------------------------===// 219 220// Alias instruction mapping movr0 to xor. 221// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 222// FIXME: Set encoding to pseudo. 223let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 224 isCodeGenOnly = 1 in 225def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", 226 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; 227 228// Other widths can also make use of the 32-bit xor, which may have a smaller 229// encoding and avoid partial register updates. 230def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 231def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 232def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> { 233 let AddedComplexity = 20; 234} 235 236// Materialize i64 constant where top 32-bits are zero. This could theoretically 237// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 238// that would make it more difficult to rematerialize. 239let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 240 isCodeGenOnly = 1, neverHasSideEffects = 1 in 241def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src), 242 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>; 243 244// This 64-bit pseudo-move can be used for both a 64-bit constant that is 245// actually the zero-extension of a 32-bit constant, and for labels in the 246// x86-64 small code model. 247def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>; 248 249let AddedComplexity = 1 in 250def : Pat<(i64 mov64imm32:$src), 251 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; 252 253// Use sbb to materialize carry bit. 254let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 255// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 256// However, Pat<> can't replicate the destination reg into the inputs of the 257// result. 258def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 259 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 260def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 261 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 262def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 263 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 264def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 265 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 266} // isCodeGenOnly 267 268 269def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 270 (SETB_C16r)>; 271def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 272 (SETB_C32r)>; 273def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 274 (SETB_C64r)>; 275 276def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 277 (SETB_C16r)>; 278def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 279 (SETB_C32r)>; 280def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 281 (SETB_C64r)>; 282 283// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 284// will be eliminated and that the sbb can be extended up to a wider type. When 285// this happens, it is great. However, if we are left with an 8-bit sbb and an 286// and, we might as well just match it as a setb. 287def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 288 (SETBr)>; 289 290// (add OP, SETB) -> (adc OP, 0) 291def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 292 (ADC8ri GR8:$op, 0)>; 293def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 294 (ADC32ri8 GR32:$op, 0)>; 295def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 296 (ADC64ri8 GR64:$op, 0)>; 297 298// (sub OP, SETB) -> (sbb OP, 0) 299def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 300 (SBB8ri GR8:$op, 0)>; 301def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 302 (SBB32ri8 GR32:$op, 0)>; 303def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 304 (SBB64ri8 GR64:$op, 0)>; 305 306// (sub OP, SETCC_CARRY) -> (adc OP, 0) 307def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 308 (ADC8ri GR8:$op, 0)>; 309def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 310 (ADC32ri8 GR32:$op, 0)>; 311def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 312 (ADC64ri8 GR64:$op, 0)>; 313 314//===----------------------------------------------------------------------===// 315// String Pseudo Instructions 316// 317let SchedRW = [WriteMicrocoded] in { 318let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 319def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 320 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 321 Requires<[In32BitMode]>; 322def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 323 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize, 324 Requires<[In32BitMode]>; 325def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 326 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, 327 Requires<[In32BitMode]>; 328} 329 330let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 331def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 332 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 333 Requires<[In64BitMode]>; 334def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 335 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize, 336 Requires<[In64BitMode]>; 337def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 338 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, 339 Requires<[In64BitMode]>; 340def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 341 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 342 Requires<[In64BitMode]>; 343} 344 345// FIXME: Should use "(X86rep_stos AL)" as the pattern. 346let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 347 let Uses = [AL,ECX,EDI] in 348 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 349 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 350 Requires<[In32BitMode]>; 351 let Uses = [AX,ECX,EDI] in 352 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 353 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize, 354 Requires<[In32BitMode]>; 355 let Uses = [EAX,ECX,EDI] in 356 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 357 [(X86rep_stos i32)], IIC_REP_STOS>, REP, 358 Requires<[In32BitMode]>; 359} 360 361let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 362 let Uses = [AL,RCX,RDI] in 363 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 364 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 365 Requires<[In64BitMode]>; 366 let Uses = [AX,RCX,RDI] in 367 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 368 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize, 369 Requires<[In64BitMode]>; 370 let Uses = [RAX,RCX,RDI] in 371 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 372 [(X86rep_stos i32)], IIC_REP_STOS>, REP, 373 Requires<[In64BitMode]>; 374 375 let Uses = [RAX,RCX,RDI] in 376 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 377 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 378 Requires<[In64BitMode]>; 379} 380} // SchedRW 381 382//===----------------------------------------------------------------------===// 383// Thread Local Storage Instructions 384// 385 386// ELF TLS Support 387// All calls clobber the non-callee saved registers. ESP is marked as 388// a use to prevent stack-pointer assignments that appear immediately 389// before calls from potentially appearing dead. 390let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, 391 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 392 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 393 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 394 Uses = [ESP] in { 395def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 396 "# TLS_addr32", 397 [(X86tlsaddr tls32addr:$sym)]>, 398 Requires<[In32BitMode]>; 399def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 400 "# TLS_base_addr32", 401 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 402 Requires<[In32BitMode]>; 403} 404 405// All calls clobber the non-callee saved registers. RSP is marked as 406// a use to prevent stack-pointer assignments that appear immediately 407// before calls from potentially appearing dead. 408let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 409 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, 410 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 411 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 412 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 413 Uses = [RSP] in { 414def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 415 "# TLS_addr64", 416 [(X86tlsaddr tls64addr:$sym)]>, 417 Requires<[In64BitMode]>; 418def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 419 "# TLS_base_addr64", 420 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 421 Requires<[In64BitMode]>; 422} 423 424// Darwin TLS Support 425// For i386, the address of the thunk is passed on the stack, on return the 426// address of the variable is in %eax. %ecx is trashed during the function 427// call. All other registers are preserved. 428let Defs = [EAX, ECX, EFLAGS], 429 Uses = [ESP], 430 usesCustomInserter = 1 in 431def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 432 "# TLSCall_32", 433 [(X86TLSCall addr:$sym)]>, 434 Requires<[In32BitMode]>; 435 436// For x86_64, the address of the thunk is passed in %rdi, on return 437// the address of the variable is in %rax. All other registers are preserved. 438let Defs = [RAX, EFLAGS], 439 Uses = [RSP, RDI], 440 usesCustomInserter = 1 in 441def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 442 "# TLSCall_64", 443 [(X86TLSCall addr:$sym)]>, 444 Requires<[In64BitMode]>; 445 446 447//===----------------------------------------------------------------------===// 448// Conditional Move Pseudo Instructions 449 450// X86 doesn't have 8-bit conditional moves. Use a customInserter to 451// emit control flow. An alternative to this is to mark i8 SELECT as Promote, 452// however that requires promoting the operands, and can induce additional 453// i8 register pressure. 454let usesCustomInserter = 1, Uses = [EFLAGS] in { 455def CMOV_GR8 : I<0, Pseudo, 456 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), 457 "#CMOV_GR8 PSEUDO!", 458 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, 459 imm:$cond, EFLAGS))]>; 460 461let Predicates = [NoCMov] in { 462def CMOV_GR32 : I<0, Pseudo, 463 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond), 464 "#CMOV_GR32* PSEUDO!", 465 [(set GR32:$dst, 466 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>; 467def CMOV_GR16 : I<0, Pseudo, 468 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond), 469 "#CMOV_GR16* PSEUDO!", 470 [(set GR16:$dst, 471 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>; 472} // Predicates = [NoCMov] 473 474// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 475// SSE1. 476let Predicates = [FPStackf32] in 477def CMOV_RFP32 : I<0, Pseudo, 478 (outs RFP32:$dst), 479 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond), 480 "#CMOV_RFP32 PSEUDO!", 481 [(set RFP32:$dst, 482 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond, 483 EFLAGS))]>; 484// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 485// SSE2. 486let Predicates = [FPStackf64] in 487def CMOV_RFP64 : I<0, Pseudo, 488 (outs RFP64:$dst), 489 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond), 490 "#CMOV_RFP64 PSEUDO!", 491 [(set RFP64:$dst, 492 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond, 493 EFLAGS))]>; 494def CMOV_RFP80 : I<0, Pseudo, 495 (outs RFP80:$dst), 496 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond), 497 "#CMOV_RFP80 PSEUDO!", 498 [(set RFP80:$dst, 499 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond, 500 EFLAGS))]>; 501} // UsesCustomInserter = 1, Uses = [EFLAGS] 502 503 504//===----------------------------------------------------------------------===// 505// Atomic Instruction Pseudo Instructions 506//===----------------------------------------------------------------------===// 507 508// Pseudo atomic instructions 509 510multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> { 511 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in { 512 let Defs = [EFLAGS, AL] in 513 def NAME#8 : I<0, Pseudo, (outs GR8:$dst), 514 (ins i8mem:$ptr, GR8:$val), 515 !strconcat(mnemonic, "8 PSEUDO!"), []>; 516 let Defs = [EFLAGS, AX] in 517 def NAME#16 : I<0, Pseudo,(outs GR16:$dst), 518 (ins i16mem:$ptr, GR16:$val), 519 !strconcat(mnemonic, "16 PSEUDO!"), []>; 520 let Defs = [EFLAGS, EAX] in 521 def NAME#32 : I<0, Pseudo, (outs GR32:$dst), 522 (ins i32mem:$ptr, GR32:$val), 523 !strconcat(mnemonic, "32 PSEUDO!"), []>; 524 let Defs = [EFLAGS, RAX] in 525 def NAME#64 : I<0, Pseudo, (outs GR64:$dst), 526 (ins i64mem:$ptr, GR64:$val), 527 !strconcat(mnemonic, "64 PSEUDO!"), []>; 528 } 529} 530 531multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> { 532 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val), 533 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>; 534 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val), 535 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>; 536 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val), 537 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>; 538 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val), 539 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>; 540} 541 542// Atomic exchange, and, or, xor 543defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">; 544defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">; 545defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">; 546defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">; 547defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">; 548defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">; 549defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">; 550defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">; 551 552defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">; 553defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">; 554defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">; 555defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">; 556defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">; 557defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">; 558defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">; 559defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">; 560 561multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> { 562 let usesCustomInserter = 1, Defs = [EFLAGS, EAX, EDX], 563 mayLoad = 1, mayStore = 1, hasSideEffects = 0 in 564 def NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 565 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 566 !strconcat(mnemonic, "6432 PSEUDO!"), []>; 567} 568 569defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">; 570defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">; 571defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">; 572defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">; 573defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">; 574defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">; 575defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">; 576defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">; 577defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">; 578defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">; 579defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">; 580 581//===----------------------------------------------------------------------===// 582// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 583//===----------------------------------------------------------------------===// 584 585// FIXME: Use normal instructions and add lock prefix dynamically. 586 587// Memory barriers 588 589// TODO: Get this to fold the constant into the instruction. 590let isCodeGenOnly = 1, Defs = [EFLAGS] in 591def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 592 "or{l}\t{$zero, $dst|$dst, $zero}", 593 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK, 594 Sched<[WriteALULd, WriteRMW]>; 595 596let hasSideEffects = 1 in 597def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 598 "#MEMBARRIER", 599 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 600 601// RegOpc corresponds to the mr version of the instruction 602// ImmOpc corresponds to the mi version of the instruction 603// ImmOpc8 corresponds to the mi8 version of the instruction 604// ImmMod corresponds to the instruction format of the mi and mi8 versions 605multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 606 Format ImmMod, string mnemonic> { 607let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 608 SchedRW = [WriteALULd, WriteRMW] in { 609 610def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 611 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 612 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 613 !strconcat(mnemonic, "{b}\t", 614 "{$src2, $dst|$dst, $src2}"), 615 [], IIC_ALU_NONMEM>, LOCK; 616def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 617 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 618 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 619 !strconcat(mnemonic, "{w}\t", 620 "{$src2, $dst|$dst, $src2}"), 621 [], IIC_ALU_NONMEM>, OpSize, LOCK; 622def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 623 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 624 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 625 !strconcat(mnemonic, "{l}\t", 626 "{$src2, $dst|$dst, $src2}"), 627 [], IIC_ALU_NONMEM>, LOCK; 628def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 629 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 630 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 631 !strconcat(mnemonic, "{q}\t", 632 "{$src2, $dst|$dst, $src2}"), 633 [], IIC_ALU_NONMEM>, LOCK; 634 635def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 636 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 637 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 638 !strconcat(mnemonic, "{b}\t", 639 "{$src2, $dst|$dst, $src2}"), 640 [], IIC_ALU_MEM>, LOCK; 641 642def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 643 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 644 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 645 !strconcat(mnemonic, "{w}\t", 646 "{$src2, $dst|$dst, $src2}"), 647 [], IIC_ALU_MEM>, OpSize, LOCK; 648 649def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 650 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 651 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 652 !strconcat(mnemonic, "{l}\t", 653 "{$src2, $dst|$dst, $src2}"), 654 [], IIC_ALU_MEM>, LOCK; 655 656def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 657 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 658 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 659 !strconcat(mnemonic, "{q}\t", 660 "{$src2, $dst|$dst, $src2}"), 661 [], IIC_ALU_MEM>, LOCK; 662 663def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 664 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 665 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 666 !strconcat(mnemonic, "{w}\t", 667 "{$src2, $dst|$dst, $src2}"), 668 [], IIC_ALU_MEM>, OpSize, LOCK; 669def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 670 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 671 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 672 !strconcat(mnemonic, "{l}\t", 673 "{$src2, $dst|$dst, $src2}"), 674 [], IIC_ALU_MEM>, LOCK; 675def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 676 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 677 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 678 !strconcat(mnemonic, "{q}\t", 679 "{$src2, $dst|$dst, $src2}"), 680 [], IIC_ALU_MEM>, LOCK; 681 682} 683 684} 685 686defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 687defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 688defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 689defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 690defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 691 692// Optimized codegen when the non-memory output is not used. 693multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 694 string mnemonic> { 695let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 696 SchedRW = [WriteALULd, WriteRMW] in { 697 698def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 699 !strconcat(mnemonic, "{b}\t$dst"), 700 [], IIC_UNARY_MEM>, LOCK; 701def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 702 !strconcat(mnemonic, "{w}\t$dst"), 703 [], IIC_UNARY_MEM>, OpSize, LOCK; 704def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 705 !strconcat(mnemonic, "{l}\t$dst"), 706 [], IIC_UNARY_MEM>, LOCK; 707def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 708 !strconcat(mnemonic, "{q}\t$dst"), 709 [], IIC_UNARY_MEM>, LOCK; 710} 711} 712 713defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">; 714defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">; 715 716// Atomic compare and swap. 717multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 718 SDPatternOperator frag, X86MemOperand x86memop, 719 InstrItinClass itin> { 720let isCodeGenOnly = 1 in { 721 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 722 !strconcat(mnemonic, "\t$ptr"), 723 [(frag addr:$ptr)], itin>, TB, LOCK; 724} 725} 726 727multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 728 string mnemonic, SDPatternOperator frag, 729 InstrItinClass itin8, InstrItinClass itin> { 730let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { 731 let Defs = [AL, EFLAGS], Uses = [AL] in 732 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 733 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 734 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 735 let Defs = [AX, EFLAGS], Uses = [AX] in 736 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 737 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 738 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK; 739 let Defs = [EAX, EFLAGS], Uses = [EAX] in 740 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 741 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 742 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK; 743 let Defs = [RAX, EFLAGS], Uses = [RAX] in 744 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 745 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 746 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 747} 748} 749 750let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 751 SchedRW = [WriteALULd, WriteRMW] in { 752defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 753 X86cas8, i64mem, 754 IIC_CMPX_LOCK_8B>; 755} 756 757let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 758 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { 759defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 760 X86cas16, i128mem, 761 IIC_CMPX_LOCK_16B>, REX_W; 762} 763 764defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 765 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 766 767// Atomic exchange and add 768multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 769 string frag, 770 InstrItinClass itin8, InstrItinClass itin> { 771 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 772 SchedRW = [WriteALULd, WriteRMW] in { 773 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 774 (ins GR8:$val, i8mem:$ptr), 775 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 776 [(set GR8:$dst, 777 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 778 itin8>; 779 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 780 (ins GR16:$val, i16mem:$ptr), 781 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 782 [(set 783 GR16:$dst, 784 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 785 itin>, OpSize; 786 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 787 (ins GR32:$val, i32mem:$ptr), 788 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 789 [(set 790 GR32:$dst, 791 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 792 itin>; 793 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 794 (ins GR64:$val, i64mem:$ptr), 795 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 796 [(set 797 GR64:$dst, 798 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 799 itin>; 800 } 801} 802 803defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 804 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 805 TB, LOCK; 806 807def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 808 "#ACQUIRE_MOV PSEUDO!", 809 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 810def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 811 "#ACQUIRE_MOV PSEUDO!", 812 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 813def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 814 "#ACQUIRE_MOV PSEUDO!", 815 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 816def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 817 "#ACQUIRE_MOV PSEUDO!", 818 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 819 820def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 821 "#RELEASE_MOV PSEUDO!", 822 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 823def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 824 "#RELEASE_MOV PSEUDO!", 825 [(atomic_store_16 addr:$dst, GR16:$src)]>; 826def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 827 "#RELEASE_MOV PSEUDO!", 828 [(atomic_store_32 addr:$dst, GR32:$src)]>; 829def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 830 "#RELEASE_MOV PSEUDO!", 831 [(atomic_store_64 addr:$dst, GR64:$src)]>; 832 833//===----------------------------------------------------------------------===// 834// Conditional Move Pseudo Instructions. 835//===----------------------------------------------------------------------===// 836 837 838// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after 839// instruction selection into a branch sequence. 840let Uses = [EFLAGS], usesCustomInserter = 1 in { 841 def CMOV_FR32 : I<0, Pseudo, 842 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), 843 "#CMOV_FR32 PSEUDO!", 844 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, 845 EFLAGS))]>; 846 def CMOV_FR64 : I<0, Pseudo, 847 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), 848 "#CMOV_FR64 PSEUDO!", 849 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, 850 EFLAGS))]>; 851 def CMOV_V4F32 : I<0, Pseudo, 852 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 853 "#CMOV_V4F32 PSEUDO!", 854 [(set VR128:$dst, 855 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, 856 EFLAGS)))]>; 857 def CMOV_V2F64 : I<0, Pseudo, 858 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 859 "#CMOV_V2F64 PSEUDO!", 860 [(set VR128:$dst, 861 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 862 EFLAGS)))]>; 863 def CMOV_V2I64 : I<0, Pseudo, 864 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 865 "#CMOV_V2I64 PSEUDO!", 866 [(set VR128:$dst, 867 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 868 EFLAGS)))]>; 869 def CMOV_V8F32 : I<0, Pseudo, 870 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 871 "#CMOV_V8F32 PSEUDO!", 872 [(set VR256:$dst, 873 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, 874 EFLAGS)))]>; 875 def CMOV_V4F64 : I<0, Pseudo, 876 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 877 "#CMOV_V4F64 PSEUDO!", 878 [(set VR256:$dst, 879 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 880 EFLAGS)))]>; 881 def CMOV_V4I64 : I<0, Pseudo, 882 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 883 "#CMOV_V4I64 PSEUDO!", 884 [(set VR256:$dst, 885 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 886 EFLAGS)))]>; 887} 888 889 890//===----------------------------------------------------------------------===// 891// DAG Pattern Matching Rules 892//===----------------------------------------------------------------------===// 893 894// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 895def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 896def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 897def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 898def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 899def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 900def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 901 902def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 903 (ADD32ri GR32:$src1, tconstpool:$src2)>; 904def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 905 (ADD32ri GR32:$src1, tjumptable:$src2)>; 906def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 907 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 908def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 909 (ADD32ri GR32:$src1, texternalsym:$src2)>; 910def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 911 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 912 913def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 914 (MOV32mi addr:$dst, tglobaladdr:$src)>; 915def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 916 (MOV32mi addr:$dst, texternalsym:$src)>; 917def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 918 (MOV32mi addr:$dst, tblockaddress:$src)>; 919 920 921 922// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 923// code model mode, should use 'movabs'. FIXME: This is really a hack, the 924// 'movabs' predicate should handle this sort of thing. 925def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 926 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 927def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 928 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 929def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 930 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 931def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 932 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 933def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 934 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 935 936// In kernel code model, we can get the address of a label 937// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 938// the MOV64ri32 should accept these. 939def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 940 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 941def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 942 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 943def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 944 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 945def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 946 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 947def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 948 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 949 950// If we have small model and -static mode, it is safe to store global addresses 951// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 952// for MOV64mi32 should handle this sort of thing. 953def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 954 (MOV64mi32 addr:$dst, tconstpool:$src)>, 955 Requires<[NearData, IsStatic]>; 956def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 957 (MOV64mi32 addr:$dst, tjumptable:$src)>, 958 Requires<[NearData, IsStatic]>; 959def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 960 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 961 Requires<[NearData, IsStatic]>; 962def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 963 (MOV64mi32 addr:$dst, texternalsym:$src)>, 964 Requires<[NearData, IsStatic]>; 965def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 966 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 967 Requires<[NearData, IsStatic]>; 968 969 970 971// Calls 972 973// tls has some funny stuff here... 974// This corresponds to movabs $foo@tpoff, %rax 975def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 976 (MOV64ri tglobaltlsaddr :$dst)>; 977// This corresponds to add $foo@tpoff, %rax 978def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 979 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 980 981 982// Direct PC relative function call for small code model. 32-bit displacement 983// sign extended to 64-bit. 984def : Pat<(X86call (i64 tglobaladdr:$dst)), 985 (CALL64pcrel32 tglobaladdr:$dst)>; 986def : Pat<(X86call (i64 texternalsym:$dst)), 987 (CALL64pcrel32 texternalsym:$dst)>; 988 989// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 990// can never use callee-saved registers. That is the purpose of the GR64_TC 991// register classes. 992// 993// The only volatile register that is never used by the calling convention is 994// %r11. This happens when calling a vararg function with 6 arguments. 995// 996// Match an X86tcret that uses less than 7 volatile registers. 997def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 998 (X86tcret node:$ptr, node:$off), [{ 999 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1000 unsigned NumRegs = 0; 1001 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1002 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1003 return false; 1004 return true; 1005}]>; 1006 1007def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1008 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1009 Requires<[In32BitMode]>; 1010 1011// FIXME: This is disabled for 32-bit PIC mode because the global base 1012// register which is part of the address mode may be assigned a 1013// callee-saved register. 1014def : Pat<(X86tcret (load addr:$dst), imm:$off), 1015 (TCRETURNmi addr:$dst, imm:$off)>, 1016 Requires<[In32BitMode, IsNotPIC]>; 1017 1018def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1019 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1020 Requires<[In32BitMode]>; 1021 1022def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1023 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1024 Requires<[In32BitMode]>; 1025 1026def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1027 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1028 Requires<[In64BitMode]>; 1029 1030// Don't fold loads into X86tcret requiring more than 6 regs. 1031// There wouldn't be enough scratch registers for base+index. 1032def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1033 (TCRETURNmi64 addr:$dst, imm:$off)>, 1034 Requires<[In64BitMode]>; 1035 1036def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1037 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1038 Requires<[In64BitMode]>; 1039 1040def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1041 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1042 Requires<[In64BitMode]>; 1043 1044// Normal calls, with various flavors of addresses. 1045def : Pat<(X86call (i32 tglobaladdr:$dst)), 1046 (CALLpcrel32 tglobaladdr:$dst)>; 1047def : Pat<(X86call (i32 texternalsym:$dst)), 1048 (CALLpcrel32 texternalsym:$dst)>; 1049def : Pat<(X86call (i32 imm:$dst)), 1050 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1051 1052// Comparisons. 1053 1054// TEST R,R is smaller than CMP R,0 1055def : Pat<(X86cmp GR8:$src1, 0), 1056 (TEST8rr GR8:$src1, GR8:$src1)>; 1057def : Pat<(X86cmp GR16:$src1, 0), 1058 (TEST16rr GR16:$src1, GR16:$src1)>; 1059def : Pat<(X86cmp GR32:$src1, 0), 1060 (TEST32rr GR32:$src1, GR32:$src1)>; 1061def : Pat<(X86cmp GR64:$src1, 0), 1062 (TEST64rr GR64:$src1, GR64:$src1)>; 1063 1064// Conditional moves with folded loads with operands swapped and conditions 1065// inverted. 1066multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1067 Instruction Inst64> { 1068 let Predicates = [HasCMov] in { 1069 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1070 (Inst16 GR16:$src2, addr:$src1)>; 1071 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1072 (Inst32 GR32:$src2, addr:$src1)>; 1073 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1074 (Inst64 GR64:$src2, addr:$src1)>; 1075 } 1076} 1077 1078defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1079defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1080defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1081defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1082defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1083defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1084defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1085defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1086defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1087defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1088defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1089defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1090defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1091defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1092defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1093defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1094 1095// zextload bool -> zextload byte 1096def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1097def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1098def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1099def : Pat<(zextloadi64i1 addr:$src), 1100 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1101 1102// extload bool -> extload byte 1103// When extloading from 16-bit and smaller memory locations into 64-bit 1104// registers, use zero-extending loads so that the entire 64-bit register is 1105// defined, avoiding partial-register updates. 1106 1107def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1108def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1109def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1110def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1111def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1112def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1113 1114// For other extloads, use subregs, since the high contents of the register are 1115// defined after an extload. 1116def : Pat<(extloadi64i1 addr:$src), 1117 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1118def : Pat<(extloadi64i8 addr:$src), 1119 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1120def : Pat<(extloadi64i16 addr:$src), 1121 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1122def : Pat<(extloadi64i32 addr:$src), 1123 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1124 1125// anyext. Define these to do an explicit zero-extend to 1126// avoid partial-register updates. 1127def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1128 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1129def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1130 1131// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1132def : Pat<(i32 (anyext GR16:$src)), 1133 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1134 1135def : Pat<(i64 (anyext GR8 :$src)), 1136 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1137def : Pat<(i64 (anyext GR16:$src)), 1138 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1139def : Pat<(i64 (anyext GR32:$src)), 1140 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1141 1142 1143// Any instruction that defines a 32-bit result leaves the high half of the 1144// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1145// be copying from a truncate. And x86's cmov doesn't do anything if the 1146// condition is false. But any other 32-bit operation will zero-extend 1147// up to 64 bits. 1148def def32 : PatLeaf<(i32 GR32:$src), [{ 1149 return N->getOpcode() != ISD::TRUNCATE && 1150 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1151 N->getOpcode() != ISD::CopyFromReg && 1152 N->getOpcode() != X86ISD::CMOV; 1153}]>; 1154 1155// In the case of a 32-bit def that is known to implicitly zero-extend, 1156// we can use a SUBREG_TO_REG. 1157def : Pat<(i64 (zext def32:$src)), 1158 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1159 1160//===----------------------------------------------------------------------===// 1161// Pattern match OR as ADD 1162//===----------------------------------------------------------------------===// 1163 1164// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1165// 3-addressified into an LEA instruction to avoid copies. However, we also 1166// want to finally emit these instructions as an or at the end of the code 1167// generator to make the generated code easier to read. To do this, we select 1168// into "disjoint bits" pseudo ops. 1169 1170// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1171def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1172 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1173 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1174 1175 APInt KnownZero0, KnownOne0; 1176 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1177 APInt KnownZero1, KnownOne1; 1178 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1179 return (~KnownZero0 & ~KnownZero1) == 0; 1180}]>; 1181 1182 1183// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1184// Try this before the selecting to OR. 1185let AddedComplexity = 5, SchedRW = [WriteALU] in { 1186 1187let isConvertibleToThreeAddress = 1, 1188 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1189let isCommutable = 1 in { 1190def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1191 "", // orw/addw REG, REG 1192 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1193def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1194 "", // orl/addl REG, REG 1195 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1196def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1197 "", // orq/addq REG, REG 1198 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1199} // isCommutable 1200 1201// NOTE: These are order specific, we want the ri8 forms to be listed 1202// first so that they are slightly preferred to the ri forms. 1203 1204def ADD16ri8_DB : I<0, Pseudo, 1205 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1206 "", // orw/addw REG, imm8 1207 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1208def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1209 "", // orw/addw REG, imm 1210 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1211 1212def ADD32ri8_DB : I<0, Pseudo, 1213 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1214 "", // orl/addl REG, imm8 1215 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1216def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1217 "", // orl/addl REG, imm 1218 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1219 1220 1221def ADD64ri8_DB : I<0, Pseudo, 1222 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1223 "", // orq/addq REG, imm8 1224 [(set GR64:$dst, (or_is_add GR64:$src1, 1225 i64immSExt8:$src2))]>; 1226def ADD64ri32_DB : I<0, Pseudo, 1227 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1228 "", // orq/addq REG, imm 1229 [(set GR64:$dst, (or_is_add GR64:$src1, 1230 i64immSExt32:$src2))]>; 1231} 1232} // AddedComplexity, SchedRW 1233 1234 1235//===----------------------------------------------------------------------===// 1236// Some peepholes 1237//===----------------------------------------------------------------------===// 1238 1239// Odd encoding trick: -128 fits into an 8-bit immediate field while 1240// +128 doesn't, so in this special case use a sub instead of an add. 1241def : Pat<(add GR16:$src1, 128), 1242 (SUB16ri8 GR16:$src1, -128)>; 1243def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1244 (SUB16mi8 addr:$dst, -128)>; 1245 1246def : Pat<(add GR32:$src1, 128), 1247 (SUB32ri8 GR32:$src1, -128)>; 1248def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1249 (SUB32mi8 addr:$dst, -128)>; 1250 1251def : Pat<(add GR64:$src1, 128), 1252 (SUB64ri8 GR64:$src1, -128)>; 1253def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1254 (SUB64mi8 addr:$dst, -128)>; 1255 1256// The same trick applies for 32-bit immediate fields in 64-bit 1257// instructions. 1258def : Pat<(add GR64:$src1, 0x0000000080000000), 1259 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1260def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1261 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1262 1263// To avoid needing to materialize an immediate in a register, use a 32-bit and 1264// with implicit zero-extension instead of a 64-bit and if the immediate has at 1265// least 32 bits of leading zeros. If in addition the last 32 bits can be 1266// represented with a sign extension of a 8 bit constant, use that. 1267 1268def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1269 (SUBREG_TO_REG 1270 (i64 0), 1271 (AND32ri8 1272 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1273 (i32 (GetLo8XForm imm:$imm))), 1274 sub_32bit)>; 1275 1276def : Pat<(and GR64:$src, i64immZExt32:$imm), 1277 (SUBREG_TO_REG 1278 (i64 0), 1279 (AND32ri 1280 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1281 (i32 (GetLo32XForm imm:$imm))), 1282 sub_32bit)>; 1283 1284 1285// r & (2^16-1) ==> movz 1286def : Pat<(and GR32:$src1, 0xffff), 1287 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1288// r & (2^8-1) ==> movz 1289def : Pat<(and GR32:$src1, 0xff), 1290 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1291 GR32_ABCD)), 1292 sub_8bit))>, 1293 Requires<[In32BitMode]>; 1294// r & (2^8-1) ==> movz 1295def : Pat<(and GR16:$src1, 0xff), 1296 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1297 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1298 sub_16bit)>, 1299 Requires<[In32BitMode]>; 1300 1301// r & (2^32-1) ==> movz 1302def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1303 (SUBREG_TO_REG (i64 0), 1304 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1305 sub_32bit)>; 1306// r & (2^16-1) ==> movz 1307def : Pat<(and GR64:$src, 0xffff), 1308 (SUBREG_TO_REG (i64 0), 1309 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1310 sub_32bit)>; 1311// r & (2^8-1) ==> movz 1312def : Pat<(and GR64:$src, 0xff), 1313 (SUBREG_TO_REG (i64 0), 1314 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1315 sub_32bit)>; 1316// r & (2^8-1) ==> movz 1317def : Pat<(and GR32:$src1, 0xff), 1318 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1319 Requires<[In64BitMode]>; 1320// r & (2^8-1) ==> movz 1321def : Pat<(and GR16:$src1, 0xff), 1322 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1323 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1324 Requires<[In64BitMode]>; 1325 1326 1327// sext_inreg patterns 1328def : Pat<(sext_inreg GR32:$src, i16), 1329 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1330def : Pat<(sext_inreg GR32:$src, i8), 1331 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1332 GR32_ABCD)), 1333 sub_8bit))>, 1334 Requires<[In32BitMode]>; 1335 1336def : Pat<(sext_inreg GR16:$src, i8), 1337 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1338 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1339 sub_16bit)>, 1340 Requires<[In32BitMode]>; 1341 1342def : Pat<(sext_inreg GR64:$src, i32), 1343 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1344def : Pat<(sext_inreg GR64:$src, i16), 1345 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1346def : Pat<(sext_inreg GR64:$src, i8), 1347 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1348def : Pat<(sext_inreg GR32:$src, i8), 1349 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1350 Requires<[In64BitMode]>; 1351def : Pat<(sext_inreg GR16:$src, i8), 1352 (EXTRACT_SUBREG (MOVSX32rr8 1353 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1354 Requires<[In64BitMode]>; 1355 1356// sext, sext_load, zext, zext_load 1357def: Pat<(i16 (sext GR8:$src)), 1358 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1359def: Pat<(sextloadi16i8 addr:$src), 1360 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1361def: Pat<(i16 (zext GR8:$src)), 1362 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1363def: Pat<(zextloadi16i8 addr:$src), 1364 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1365 1366// trunc patterns 1367def : Pat<(i16 (trunc GR32:$src)), 1368 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1369def : Pat<(i8 (trunc GR32:$src)), 1370 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1371 sub_8bit)>, 1372 Requires<[In32BitMode]>; 1373def : Pat<(i8 (trunc GR16:$src)), 1374 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1375 sub_8bit)>, 1376 Requires<[In32BitMode]>; 1377def : Pat<(i32 (trunc GR64:$src)), 1378 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1379def : Pat<(i16 (trunc GR64:$src)), 1380 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1381def : Pat<(i8 (trunc GR64:$src)), 1382 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1383def : Pat<(i8 (trunc GR32:$src)), 1384 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1385 Requires<[In64BitMode]>; 1386def : Pat<(i8 (trunc GR16:$src)), 1387 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1388 Requires<[In64BitMode]>; 1389 1390// h-register tricks 1391def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1392 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1393 sub_8bit_hi)>, 1394 Requires<[In32BitMode]>; 1395def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1396 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1397 sub_8bit_hi)>, 1398 Requires<[In32BitMode]>; 1399def : Pat<(srl GR16:$src, (i8 8)), 1400 (EXTRACT_SUBREG 1401 (MOVZX32rr8 1402 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1403 sub_8bit_hi)), 1404 sub_16bit)>, 1405 Requires<[In32BitMode]>; 1406def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1407 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1408 GR16_ABCD)), 1409 sub_8bit_hi))>, 1410 Requires<[In32BitMode]>; 1411def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1412 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1413 GR16_ABCD)), 1414 sub_8bit_hi))>, 1415 Requires<[In32BitMode]>; 1416def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1417 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1418 GR32_ABCD)), 1419 sub_8bit_hi))>, 1420 Requires<[In32BitMode]>; 1421def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1422 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1423 GR32_ABCD)), 1424 sub_8bit_hi))>, 1425 Requires<[In32BitMode]>; 1426 1427// h-register tricks. 1428// For now, be conservative on x86-64 and use an h-register extract only if the 1429// value is immediately zero-extended or stored, which are somewhat common 1430// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1431// from being allocated in the same instruction as the h register, as there's 1432// currently no way to describe this requirement to the register allocator. 1433 1434// h-register extract and zero-extend. 1435def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1436 (SUBREG_TO_REG 1437 (i64 0), 1438 (MOVZX32_NOREXrr8 1439 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1440 sub_8bit_hi)), 1441 sub_32bit)>; 1442def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1443 (MOVZX32_NOREXrr8 1444 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1445 sub_8bit_hi))>, 1446 Requires<[In64BitMode]>; 1447def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1448 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1449 GR32_ABCD)), 1450 sub_8bit_hi))>, 1451 Requires<[In64BitMode]>; 1452def : Pat<(srl GR16:$src, (i8 8)), 1453 (EXTRACT_SUBREG 1454 (MOVZX32_NOREXrr8 1455 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1456 sub_8bit_hi)), 1457 sub_16bit)>, 1458 Requires<[In64BitMode]>; 1459def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1460 (MOVZX32_NOREXrr8 1461 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1462 sub_8bit_hi))>, 1463 Requires<[In64BitMode]>; 1464def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1465 (MOVZX32_NOREXrr8 1466 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1467 sub_8bit_hi))>, 1468 Requires<[In64BitMode]>; 1469def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1470 (SUBREG_TO_REG 1471 (i64 0), 1472 (MOVZX32_NOREXrr8 1473 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1474 sub_8bit_hi)), 1475 sub_32bit)>; 1476def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1477 (SUBREG_TO_REG 1478 (i64 0), 1479 (MOVZX32_NOREXrr8 1480 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1481 sub_8bit_hi)), 1482 sub_32bit)>; 1483 1484// h-register extract and store. 1485def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1486 (MOV8mr_NOREX 1487 addr:$dst, 1488 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1489 sub_8bit_hi))>; 1490def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1491 (MOV8mr_NOREX 1492 addr:$dst, 1493 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1494 sub_8bit_hi))>, 1495 Requires<[In64BitMode]>; 1496def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1497 (MOV8mr_NOREX 1498 addr:$dst, 1499 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1500 sub_8bit_hi))>, 1501 Requires<[In64BitMode]>; 1502 1503 1504// (shl x, 1) ==> (add x, x) 1505// Note that if x is undef (immediate or otherwise), we could theoretically 1506// end up with the two uses of x getting different values, producing a result 1507// where the least significant bit is not 0. However, the probability of this 1508// happening is considered low enough that this is officially not a 1509// "real problem". 1510def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1511def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1512def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1513def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1514 1515// Helper imms that check if a mask doesn't change significant shift bits. 1516def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>; 1517def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>; 1518 1519// (shl x (and y, 31)) ==> (shl x, y) 1520def : Pat<(shl GR8:$src1, (and CL, immShift32)), 1521 (SHL8rCL GR8:$src1)>; 1522def : Pat<(shl GR16:$src1, (and CL, immShift32)), 1523 (SHL16rCL GR16:$src1)>; 1524def : Pat<(shl GR32:$src1, (and CL, immShift32)), 1525 (SHL32rCL GR32:$src1)>; 1526def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1527 (SHL8mCL addr:$dst)>; 1528def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1529 (SHL16mCL addr:$dst)>; 1530def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1531 (SHL32mCL addr:$dst)>; 1532 1533def : Pat<(srl GR8:$src1, (and CL, immShift32)), 1534 (SHR8rCL GR8:$src1)>; 1535def : Pat<(srl GR16:$src1, (and CL, immShift32)), 1536 (SHR16rCL GR16:$src1)>; 1537def : Pat<(srl GR32:$src1, (and CL, immShift32)), 1538 (SHR32rCL GR32:$src1)>; 1539def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1540 (SHR8mCL addr:$dst)>; 1541def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1542 (SHR16mCL addr:$dst)>; 1543def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1544 (SHR32mCL addr:$dst)>; 1545 1546def : Pat<(sra GR8:$src1, (and CL, immShift32)), 1547 (SAR8rCL GR8:$src1)>; 1548def : Pat<(sra GR16:$src1, (and CL, immShift32)), 1549 (SAR16rCL GR16:$src1)>; 1550def : Pat<(sra GR32:$src1, (and CL, immShift32)), 1551 (SAR32rCL GR32:$src1)>; 1552def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1553 (SAR8mCL addr:$dst)>; 1554def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1555 (SAR16mCL addr:$dst)>; 1556def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1557 (SAR32mCL addr:$dst)>; 1558 1559// (shl x (and y, 63)) ==> (shl x, y) 1560def : Pat<(shl GR64:$src1, (and CL, immShift64)), 1561 (SHL64rCL GR64:$src1)>; 1562def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1563 (SHL64mCL addr:$dst)>; 1564 1565def : Pat<(srl GR64:$src1, (and CL, immShift64)), 1566 (SHR64rCL GR64:$src1)>; 1567def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1568 (SHR64mCL addr:$dst)>; 1569 1570def : Pat<(sra GR64:$src1, (and CL, immShift64)), 1571 (SAR64rCL GR64:$src1)>; 1572def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1573 (SAR64mCL addr:$dst)>; 1574 1575 1576// (anyext (setcc_carry)) -> (setcc_carry) 1577def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1578 (SETB_C16r)>; 1579def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1580 (SETB_C32r)>; 1581def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1582 (SETB_C32r)>; 1583 1584 1585 1586 1587//===----------------------------------------------------------------------===// 1588// EFLAGS-defining Patterns 1589//===----------------------------------------------------------------------===// 1590 1591// add reg, reg 1592def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1593def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1594def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1595 1596// add reg, mem 1597def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1598 (ADD8rm GR8:$src1, addr:$src2)>; 1599def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1600 (ADD16rm GR16:$src1, addr:$src2)>; 1601def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1602 (ADD32rm GR32:$src1, addr:$src2)>; 1603 1604// add reg, imm 1605def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1606def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1607def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1608def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1609 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1610def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1611 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1612 1613// sub reg, reg 1614def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1615def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1616def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1617 1618// sub reg, mem 1619def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1620 (SUB8rm GR8:$src1, addr:$src2)>; 1621def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1622 (SUB16rm GR16:$src1, addr:$src2)>; 1623def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1624 (SUB32rm GR32:$src1, addr:$src2)>; 1625 1626// sub reg, imm 1627def : Pat<(sub GR8:$src1, imm:$src2), 1628 (SUB8ri GR8:$src1, imm:$src2)>; 1629def : Pat<(sub GR16:$src1, imm:$src2), 1630 (SUB16ri GR16:$src1, imm:$src2)>; 1631def : Pat<(sub GR32:$src1, imm:$src2), 1632 (SUB32ri GR32:$src1, imm:$src2)>; 1633def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1634 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1635def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1636 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1637 1638// sub 0, reg 1639def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1640def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1641def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1642def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1643 1644// mul reg, reg 1645def : Pat<(mul GR16:$src1, GR16:$src2), 1646 (IMUL16rr GR16:$src1, GR16:$src2)>; 1647def : Pat<(mul GR32:$src1, GR32:$src2), 1648 (IMUL32rr GR32:$src1, GR32:$src2)>; 1649 1650// mul reg, mem 1651def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1652 (IMUL16rm GR16:$src1, addr:$src2)>; 1653def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1654 (IMUL32rm GR32:$src1, addr:$src2)>; 1655 1656// mul reg, imm 1657def : Pat<(mul GR16:$src1, imm:$src2), 1658 (IMUL16rri GR16:$src1, imm:$src2)>; 1659def : Pat<(mul GR32:$src1, imm:$src2), 1660 (IMUL32rri GR32:$src1, imm:$src2)>; 1661def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1662 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1663def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1664 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1665 1666// reg = mul mem, imm 1667def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1668 (IMUL16rmi addr:$src1, imm:$src2)>; 1669def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1670 (IMUL32rmi addr:$src1, imm:$src2)>; 1671def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1672 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1673def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1674 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1675 1676// Patterns for nodes that do not produce flags, for instructions that do. 1677 1678// addition 1679def : Pat<(add GR64:$src1, GR64:$src2), 1680 (ADD64rr GR64:$src1, GR64:$src2)>; 1681def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1682 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1683def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1684 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1685def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1686 (ADD64rm GR64:$src1, addr:$src2)>; 1687 1688// subtraction 1689def : Pat<(sub GR64:$src1, GR64:$src2), 1690 (SUB64rr GR64:$src1, GR64:$src2)>; 1691def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1692 (SUB64rm GR64:$src1, addr:$src2)>; 1693def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1694 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1695def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1696 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1697 1698// Multiply 1699def : Pat<(mul GR64:$src1, GR64:$src2), 1700 (IMUL64rr GR64:$src1, GR64:$src2)>; 1701def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1702 (IMUL64rm GR64:$src1, addr:$src2)>; 1703def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1704 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1705def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1706 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1707def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1708 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1709def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1710 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1711 1712// Increment reg. 1713def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>; 1714def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>; 1715def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1716def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>; 1717def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1718def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1719 1720// Decrement reg. 1721def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>; 1722def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>; 1723def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1724def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>; 1725def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1726def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1727 1728// or reg/reg. 1729def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1730def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1731def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1732def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1733 1734// or reg/mem 1735def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1736 (OR8rm GR8:$src1, addr:$src2)>; 1737def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1738 (OR16rm GR16:$src1, addr:$src2)>; 1739def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1740 (OR32rm GR32:$src1, addr:$src2)>; 1741def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1742 (OR64rm GR64:$src1, addr:$src2)>; 1743 1744// or reg/imm 1745def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1746def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1747def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1748def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1749 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1750def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1751 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1752def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1753 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1754def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1755 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1756 1757// xor reg/reg 1758def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1759def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1760def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1761def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1762 1763// xor reg/mem 1764def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1765 (XOR8rm GR8:$src1, addr:$src2)>; 1766def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1767 (XOR16rm GR16:$src1, addr:$src2)>; 1768def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1769 (XOR32rm GR32:$src1, addr:$src2)>; 1770def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1771 (XOR64rm GR64:$src1, addr:$src2)>; 1772 1773// xor reg/imm 1774def : Pat<(xor GR8:$src1, imm:$src2), 1775 (XOR8ri GR8:$src1, imm:$src2)>; 1776def : Pat<(xor GR16:$src1, imm:$src2), 1777 (XOR16ri GR16:$src1, imm:$src2)>; 1778def : Pat<(xor GR32:$src1, imm:$src2), 1779 (XOR32ri GR32:$src1, imm:$src2)>; 1780def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1781 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1782def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1783 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1784def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1785 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1786def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1787 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1788 1789// and reg/reg 1790def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1791def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1792def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1793def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1794 1795// and reg/mem 1796def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1797 (AND8rm GR8:$src1, addr:$src2)>; 1798def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1799 (AND16rm GR16:$src1, addr:$src2)>; 1800def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1801 (AND32rm GR32:$src1, addr:$src2)>; 1802def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1803 (AND64rm GR64:$src1, addr:$src2)>; 1804 1805// and reg/imm 1806def : Pat<(and GR8:$src1, imm:$src2), 1807 (AND8ri GR8:$src1, imm:$src2)>; 1808def : Pat<(and GR16:$src1, imm:$src2), 1809 (AND16ri GR16:$src1, imm:$src2)>; 1810def : Pat<(and GR32:$src1, imm:$src2), 1811 (AND32ri GR32:$src1, imm:$src2)>; 1812def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1813 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1814def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1815 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1816def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1817 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1818def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1819 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1820 1821// Bit scan instruction patterns to match explicit zero-undef behavior. 1822def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1823def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1824def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1825def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1826def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1827def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1828