1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Haswell to support instruction 11// scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15def HaswellModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4 17 // instructions per cycle. 18 let IssueWidth = 4; 19 let MicroOpBufferSize = 192; // Based on the reorder buffer. 20 let LoadLatency = 4; 21 let MispredictPenalty = 16; 22} 23 24let SchedModel = HaswellModel in { 25 26// Haswell can issue micro-ops to 8 different ports in one cycle. 27 28// Ports 0, 1, 5, 6 and 7 handle all computation. 29// Port 4 gets the data half of stores. Store data can be available later than 30// the store address, but since we don't model the latency of stores, we can 31// ignore that. 32// Ports 2 and 3 are identical. They handle loads and the address half of 33// stores. Port 7 can handle address calculations. 34def HWPort0 : ProcResource<1>; 35def HWPort1 : ProcResource<1>; 36def HWPort2 : ProcResource<1>; 37def HWPort3 : ProcResource<1>; 38def HWPort4 : ProcResource<1>; 39def HWPort5 : ProcResource<1>; 40def HWPort6 : ProcResource<1>; 41def HWPort7 : ProcResource<1>; 42 43// Many micro-ops are capable of issuing on multiple ports. 44def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 45def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 46def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 47def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; 48def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 49def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 50def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 51 52// 60 Entry Unified Scheduler 53def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 54 HWPort5, HWPort6, HWPort7]> { 55 let BufferSize=60; 56} 57 58// Integer division issued on port 0. 59def HWDivider : ProcResource<1>; 60 61// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 62// cycles after the memory operand. 63def : ReadAdvance<ReadAfterLd, 4>; 64 65// Many SchedWrites are defined in pairs with and without a folded load. 66// Instructions with folded loads are usually micro-fused, so they only appear 67// as two micro-ops when queued in the reservation station. 68// This multiclass defines the resource usage for variants with and without 69// folded loads. 70multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW, 71 ProcResourceKind ExePort, 72 int Lat> { 73 // Register variant is using a single cycle on ExePort. 74 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 75 76 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 77 // latency. 78 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> { 79 let Latency = !add(Lat, 4); 80 } 81} 82 83// A folded store needs a cycle on port 4 for the store data, but it does not 84// need an extra port 2/3 cycle to recompute the address. 85def : WriteRes<WriteRMW, [HWPort4]>; 86 87def : WriteRes<WriteStore, [HWPort237, HWPort4]>; 88def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; } 89def : WriteRes<WriteMove, [HWPort0156]>; 90def : WriteRes<WriteZero, []>; 91 92defm : HWWriteResPair<WriteALU, HWPort0156, 1>; 93defm : HWWriteResPair<WriteIMul, HWPort1, 3>; 94def : WriteRes<WriteIMulH, []> { let Latency = 3; } 95defm : HWWriteResPair<WriteShift, HWPort056, 1>; 96defm : HWWriteResPair<WriteJump, HWPort5, 1>; 97 98// This is for simple LEAs with one or two input operands. 99// The complex ones can only execute on port 1, and they require two cycles on 100// the port to read all inputs. We don't model that. 101def : WriteRes<WriteLEA, [HWPort15]>; 102 103// This is quite rough, latency depends on the dividend. 104def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { 105 let Latency = 25; 106 let ResourceCycles = [1, 10]; 107} 108def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> { 109 let Latency = 29; 110 let ResourceCycles = [1, 1, 10]; 111} 112 113// Scalar and vector floating point. 114defm : HWWriteResPair<WriteFAdd, HWPort1, 3>; 115defm : HWWriteResPair<WriteFMul, HWPort0, 5>; 116defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles. 117defm : HWWriteResPair<WriteFRcp, HWPort0, 5>; 118defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>; 119defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>; 120defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>; 121defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>; 122 123// Vector integer operations. 124defm : HWWriteResPair<WriteVecShift, HWPort05, 1>; 125defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>; 126defm : HWWriteResPair<WriteVecALU, HWPort15, 1>; 127defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>; 128defm : HWWriteResPair<WriteShuffle, HWPort15, 1>; 129 130def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 131def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 132} // SchedModel 133