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1; RUN: opt < %s -S | FileCheck %s
2; CHECK-NOT: {@llvm\\.palign}
3
4define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
5entry:
6  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
7  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
8  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
9  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
10  ret <4 x i32> %3
11}
12
13define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
14entry:
15  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
16  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
17  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
18  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
19  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
20  ret double %retval12
21}
22
23declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
24
25define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
26entry:
27  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
28  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
29  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
30  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
31  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
32  ret double %retval12
33}
34
35define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
36entry:
37  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
38  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
39  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
40  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
41  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
42  ret double %retval12
43}
44
45define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
46entry:
47  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
48  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
49  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
50  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
51  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
52  ret double %retval12
53}
54
55define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
56entry:
57  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
58  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
59  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
60  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
61  ret <4 x i32> %3
62}
63
64declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
65
66define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
67entry:
68  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
69  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
70  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
71  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
72  ret <4 x i32> %3
73}
74
75define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
76entry:
77  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
78  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
79  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
80  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
81  ret <4 x i32> %3
82}
83