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1; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon  | FileCheck %s
2
3; Set of tests for when the intrinsic is used.
4
5declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>)
6declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>)
7declare <2 x double> @llvm.arm.neon.vrsqrts.v2f64(<2 x double>, <2 x double>)
8
9define <2 x float> @frsqrts_from_intr_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
10; Using registers other than v0, v1 are possible, but would be odd.
11; CHECK: frsqrts v0.2s, v0.2s, v1.2s
12        %val = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %lhs, <2 x float> %rhs)
13        ret <2 x float> %val
14}
15
16define <4 x float> @frsqrts_from_intr_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
17; Using registers other than v0, v1 are possible, but would be odd.
18; CHECK: frsqrts v0.4s, v0.4s, v1.4s
19        %val = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %lhs, <4 x float> %rhs)
20        ret <4 x float> %val
21}
22
23define <2 x double> @frsqrts_from_intr_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
24; Using registers other than v0, v1 are possible, but would be odd.
25; CHECK: frsqrts v0.2d, v0.2d, v1.2d
26        %val = call <2 x double> @llvm.arm.neon.vrsqrts.v2f64(<2 x double> %lhs, <2 x double> %rhs)
27        ret <2 x double> %val
28}
29
30declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>)
31declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>)
32declare <2 x double> @llvm.arm.neon.vrecps.v2f64(<2 x double>, <2 x double>)
33
34define <2 x float> @frecps_from_intr_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
35; Using registers other than v0, v1 are possible, but would be odd.
36; CHECK: frecps v0.2s, v0.2s, v1.2s
37        %val = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %lhs, <2 x float> %rhs)
38        ret <2 x float> %val
39}
40
41define <4 x float> @frecps_from_intr_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
42; Using registers other than v0, v1 are possible, but would be odd.
43; CHECK: frecps v0.4s, v0.4s, v1.4s
44        %val = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %lhs, <4 x float> %rhs)
45        ret <4 x float> %val
46}
47
48define <2 x double> @frecps_from_intr_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
49; Using registers other than v0, v1 are possible, but would be odd.
50; CHECK: frecps v0.2d, v0.2d, v1.2d
51        %val = call <2 x double> @llvm.arm.neon.vrecps.v2f64(<2 x double> %lhs, <2 x double> %rhs)
52        ret <2 x double> %val
53}
54
55