1; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) 4declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>) 5 6define <8 x i8> @test_uhadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 7; CHECK: test_uhadd_v8i8: 8 %tmp1 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 9; CHECK: uhadd v0.8b, v0.8b, v1.8b 10 ret <8 x i8> %tmp1 11} 12 13define <8 x i8> @test_shadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 14; CHECK: test_shadd_v8i8: 15 %tmp1 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 16; CHECK: shadd v0.8b, v0.8b, v1.8b 17 ret <8 x i8> %tmp1 18} 19 20declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) 21declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>) 22 23define <16 x i8> @test_uhadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 24; CHECK: test_uhadd_v16i8: 25 %tmp1 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 26; CHECK: uhadd v0.16b, v0.16b, v1.16b 27 ret <16 x i8> %tmp1 28} 29 30define <16 x i8> @test_shadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 31; CHECK: test_shadd_v16i8: 32 %tmp1 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 33; CHECK: shadd v0.16b, v0.16b, v1.16b 34 ret <16 x i8> %tmp1 35} 36 37declare <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16>, <4 x i16>) 38declare <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16>, <4 x i16>) 39 40define <4 x i16> @test_uhadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 41; CHECK: test_uhadd_v4i16: 42 %tmp1 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 43; CHECK: uhadd v0.4h, v0.4h, v1.4h 44 ret <4 x i16> %tmp1 45} 46 47define <4 x i16> @test_shadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 48; CHECK: test_shadd_v4i16: 49 %tmp1 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 50; CHECK: shadd v0.4h, v0.4h, v1.4h 51 ret <4 x i16> %tmp1 52} 53 54declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) 55declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>) 56 57define <8 x i16> @test_uhadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 58; CHECK: test_uhadd_v8i16: 59 %tmp1 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 60; CHECK: uhadd v0.8h, v0.8h, v1.8h 61 ret <8 x i16> %tmp1 62} 63 64define <8 x i16> @test_shadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 65; CHECK: test_shadd_v8i16: 66 %tmp1 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 67; CHECK: shadd v0.8h, v0.8h, v1.8h 68 ret <8 x i16> %tmp1 69} 70 71declare <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32>, <2 x i32>) 72declare <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32>, <2 x i32>) 73 74define <2 x i32> @test_uhadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 75; CHECK: test_uhadd_v2i32: 76 %tmp1 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 77; CHECK: uhadd v0.2s, v0.2s, v1.2s 78 ret <2 x i32> %tmp1 79} 80 81define <2 x i32> @test_shadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 82; CHECK: test_shadd_v2i32: 83 %tmp1 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 84; CHECK: shadd v0.2s, v0.2s, v1.2s 85 ret <2 x i32> %tmp1 86} 87 88declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) 89declare <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32>, <4 x i32>) 90 91define <4 x i32> @test_uhadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 92; CHECK: test_uhadd_v4i32: 93 %tmp1 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 94; CHECK: uhadd v0.4s, v0.4s, v1.4s 95 ret <4 x i32> %tmp1 96} 97 98define <4 x i32> @test_shadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 99; CHECK: test_shadd_v4i32: 100 %tmp1 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 101; CHECK: shadd v0.4s, v0.4s, v1.4s 102 ret <4 x i32> %tmp1 103} 104 105 106declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) 107declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) 108 109define <8 x i8> @test_uhsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 110; CHECK: test_uhsub_v8i8: 111 %tmp1 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 112; CHECK: uhsub v0.8b, v0.8b, v1.8b 113 ret <8 x i8> %tmp1 114} 115 116define <8 x i8> @test_shsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 117; CHECK: test_shsub_v8i8: 118 %tmp1 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 119; CHECK: shsub v0.8b, v0.8b, v1.8b 120 ret <8 x i8> %tmp1 121} 122 123declare <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8>, <16 x i8>) 124declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) 125 126define <16 x i8> @test_uhsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 127; CHECK: test_uhsub_v16i8: 128 %tmp1 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 129; CHECK: uhsub v0.16b, v0.16b, v1.16b 130 ret <16 x i8> %tmp1 131} 132 133define <16 x i8> @test_shsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 134; CHECK: test_shsub_v16i8: 135 %tmp1 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 136; CHECK: shsub v0.16b, v0.16b, v1.16b 137 ret <16 x i8> %tmp1 138} 139 140declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) 141declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) 142 143define <4 x i16> @test_uhsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 144; CHECK: test_uhsub_v4i16: 145 %tmp1 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 146; CHECK: uhsub v0.4h, v0.4h, v1.4h 147 ret <4 x i16> %tmp1 148} 149 150define <4 x i16> @test_shsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 151; CHECK: test_shsub_v4i16: 152 %tmp1 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 153; CHECK: shsub v0.4h, v0.4h, v1.4h 154 ret <4 x i16> %tmp1 155} 156 157declare <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16>, <8 x i16>) 158declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) 159 160define <8 x i16> @test_uhsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 161; CHECK: test_uhsub_v8i16: 162 %tmp1 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 163; CHECK: uhsub v0.8h, v0.8h, v1.8h 164 ret <8 x i16> %tmp1 165} 166 167define <8 x i16> @test_shsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 168; CHECK: test_shsub_v8i16: 169 %tmp1 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 170; CHECK: shsub v0.8h, v0.8h, v1.8h 171 ret <8 x i16> %tmp1 172} 173 174declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) 175declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) 176 177define <2 x i32> @test_uhsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 178; CHECK: test_uhsub_v2i32: 179 %tmp1 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 180; CHECK: uhsub v0.2s, v0.2s, v1.2s 181 ret <2 x i32> %tmp1 182} 183 184define <2 x i32> @test_shsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 185; CHECK: test_shsub_v2i32: 186 %tmp1 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 187; CHECK: shsub v0.2s, v0.2s, v1.2s 188 ret <2 x i32> %tmp1 189} 190 191declare <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32>, <4 x i32>) 192declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) 193 194define <4 x i32> @test_uhsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 195; CHECK: test_uhsub_v4i32: 196 %tmp1 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 197; CHECK: uhsub v0.4s, v0.4s, v1.4s 198 ret <4 x i32> %tmp1 199} 200 201define <4 x i32> @test_shsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 202; CHECK: test_shsub_v4i32: 203 %tmp1 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 204; CHECK: shsub v0.4s, v0.4s, v1.4s 205 ret <4 x i32> %tmp1 206} 207 208