1; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s 2; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s 3; Avoid some 's' 16-bit instruction which partially update CPSR (and add false 4; dependency) when it isn't dependent on last CPSR defining instruction. 5; rdar://8928208 6 7define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { 8 entry: 9; CHECK-LABEL: t1: 10; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 11; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 12; CHECK-NEXT: muls r0, [[REG]], [[REG2]] 13 %0 = mul nsw i32 %a, %b 14 %1 = mul nsw i32 %c, %d 15 %2 = mul nsw i32 %0, %1 16 ret i32 %2 17} 18 19; Avoid partial CPSR dependency via loop backedge. 20; rdar://10357570 21define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { 22entry: 23; CHECK-LABEL: t2: 24 %tobool7 = icmp eq i32* %ptr2, null 25 br i1 %tobool7, label %while.end, label %while.body 26 27while.body: 28; CHECK: while.body 29; CHECK: mul r{{[0-9]+}} 30; CHECK-NOT: muls 31 %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] 32 %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] 33 %0 = load i32* %ptr1.addr.09, align 4 34 %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1 35 %1 = load i32* %arrayidx1, align 4 36 %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2 37 %2 = load i32* %arrayidx3, align 4 38 %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3 39 %3 = load i32* %arrayidx4, align 4 40 %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4 41 %mul = mul i32 %1, %0 42 %mul5 = mul i32 %mul, %2 43 %mul6 = mul i32 %mul5, %3 44 store i32 %mul6, i32* %ptr2.addr.08, align 4 45 %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1 46 %tobool = icmp eq i32* %incdec.ptr, null 47 br i1 %tobool, label %while.end, label %while.body 48 49while.end: 50 ret void 51} 52 53; Allow partial CPSR dependency when code size is the priority. 54; rdar://12878928 55define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { 56entry: 57; CHECK-LABEL: t3: 58 %tobool7 = icmp eq i32* %ptr2, null 59 br i1 %tobool7, label %while.end, label %while.body 60 61while.body: 62; CHECK: while.body 63; CHECK: mul r{{[0-9]+}} 64; CHECK: muls 65 %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] 66 %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] 67 %0 = load i32* %ptr1.addr.09, align 4 68 %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1 69 %1 = load i32* %arrayidx1, align 4 70 %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2 71 %2 = load i32* %arrayidx3, align 4 72 %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3 73 %3 = load i32* %arrayidx4, align 4 74 %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4 75 %mul = mul i32 %1, %0 76 %mul5 = mul i32 %mul, %2 77 %mul6 = mul i32 %mul5, %3 78 store i32 %mul6, i32* %ptr2.addr.08, align 4 79 %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1 80 %tobool = icmp eq i32* %incdec.ptr, null 81 br i1 %tobool, label %while.end, label %while.body 82 83while.end: 84 ret void 85} 86 87; Avoid producing tMOVi8 after a high-latency flag-setting operation. 88; <rdar://problem/13468102> 89define void @t4(i32* nocapture %p, double* nocapture %q) { 90entry: 91; CHECK: t4 92; CHECK: vmrs APSR_nzcv, fpscr 93; CHECK: if.then 94; CHECK-NOT: movs 95 %0 = load double* %q, align 4 96 %cmp = fcmp olt double %0, 1.000000e+01 97 %incdec.ptr1 = getelementptr inbounds i32* %p, i32 1 98 br i1 %cmp, label %if.then, label %if.else 99 100if.then: 101 store i32 7, i32* %p, align 4 102 %incdec.ptr2 = getelementptr inbounds i32* %p, i32 2 103 store i32 8, i32* %incdec.ptr1, align 4 104 store i32 9, i32* %incdec.ptr2, align 4 105 br label %if.end 106 107if.else: 108 store i32 3, i32* %p, align 4 109 %incdec.ptr5 = getelementptr inbounds i32* %p, i32 2 110 store i32 5, i32* %incdec.ptr1, align 4 111 store i32 6, i32* %incdec.ptr5, align 4 112 br label %if.end 113 114if.end: 115 ret void 116} 117