1; Test 64-bit unsigned comparison in which the second operand is a variable. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5; Check CLGR. 6define double @f1(double %a, double %b, i64 %i1, i64 %i2) { 7; CHECK-LABEL: f1: 8; CHECK: clgr %r2, %r3 9; CHECK-NEXT: jl 10; CHECK: ldr %f0, %f2 11; CHECK: br %r14 12 %cond = icmp ult i64 %i1, %i2 13 %res = select i1 %cond, double %a, double %b 14 ret double %res 15} 16 17; Check CLG with no displacement. 18define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { 19; CHECK-LABEL: f2: 20; CHECK: clg %r2, 0(%r3) 21; CHECK-NEXT: jl 22; CHECK: ldr %f0, %f2 23; CHECK: br %r14 24 %i2 = load i64 *%ptr 25 %cond = icmp ult i64 %i1, %i2 26 %res = select i1 %cond, double %a, double %b 27 ret double %res 28} 29 30; Check the high end of the aligned CLG range. 31define double @f3(double %a, double %b, i64 %i1, i64 *%base) { 32; CHECK-LABEL: f3: 33; CHECK: clg %r2, 524280(%r3) 34; CHECK-NEXT: jl 35; CHECK: ldr %f0, %f2 36; CHECK: br %r14 37 %ptr = getelementptr i64 *%base, i64 65535 38 %i2 = load i64 *%ptr 39 %cond = icmp ult i64 %i1, %i2 40 %res = select i1 %cond, double %a, double %b 41 ret double %res 42} 43 44; Check the next doubleword up, which needs separate address logic. 45; Other sequences besides this one would be OK. 46define double @f4(double %a, double %b, i64 %i1, i64 *%base) { 47; CHECK-LABEL: f4: 48; CHECK: agfi %r3, 524288 49; CHECK: clg %r2, 0(%r3) 50; CHECK-NEXT: jl 51; CHECK: ldr %f0, %f2 52; CHECK: br %r14 53 %ptr = getelementptr i64 *%base, i64 65536 54 %i2 = load i64 *%ptr 55 %cond = icmp ult i64 %i1, %i2 56 %res = select i1 %cond, double %a, double %b 57 ret double %res 58} 59 60; Check the high end of the negative aligned CLG range. 61define double @f5(double %a, double %b, i64 %i1, i64 *%base) { 62; CHECK-LABEL: f5: 63; CHECK: clg %r2, -8(%r3) 64; CHECK-NEXT: jl 65; CHECK: ldr %f0, %f2 66; CHECK: br %r14 67 %ptr = getelementptr i64 *%base, i64 -1 68 %i2 = load i64 *%ptr 69 %cond = icmp ult i64 %i1, %i2 70 %res = select i1 %cond, double %a, double %b 71 ret double %res 72} 73 74; Check the low end of the CLG range. 75define double @f6(double %a, double %b, i64 %i1, i64 *%base) { 76; CHECK-LABEL: f6: 77; CHECK: clg %r2, -524288(%r3) 78; CHECK-NEXT: jl 79; CHECK: ldr %f0, %f2 80; CHECK: br %r14 81 %ptr = getelementptr i64 *%base, i64 -65536 82 %i2 = load i64 *%ptr 83 %cond = icmp ult i64 %i1, %i2 84 %res = select i1 %cond, double %a, double %b 85 ret double %res 86} 87 88; Check the next doubleword down, which needs separate address logic. 89; Other sequences besides this one would be OK. 90define double @f7(double %a, double %b, i64 %i1, i64 *%base) { 91; CHECK-LABEL: f7: 92; CHECK: agfi %r3, -524296 93; CHECK: clg %r2, 0(%r3) 94; CHECK-NEXT: jl 95; CHECK: ldr %f0, %f2 96; CHECK: br %r14 97 %ptr = getelementptr i64 *%base, i64 -65537 98 %i2 = load i64 *%ptr 99 %cond = icmp ult i64 %i1, %i2 100 %res = select i1 %cond, double %a, double %b 101 ret double %res 102} 103 104; Check that CLG allows an index. 105define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { 106; CHECK-LABEL: f8: 107; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}}) 108; CHECK-NEXT: jl 109; CHECK: ldr %f0, %f2 110; CHECK: br %r14 111 %add1 = add i64 %base, %index 112 %add2 = add i64 %add1, 524280 113 %ptr = inttoptr i64 %add2 to i64 * 114 %i2 = load i64 *%ptr 115 %cond = icmp ult i64 %i1, %i2 116 %res = select i1 %cond, double %a, double %b 117 ret double %res 118} 119