1; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 -mcpu=corei7 | FileCheck %s 2 3; SSE2 Logical Shift Left 4 5define <8 x i16> @test_sllw_1(<8 x i16> %InVec) { 6entry: 7 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 8 ret <8 x i16> %shl 9} 10 11; CHECK-LABEL: test_sllw_1: 12; CHECK: psllw $0, %xmm0 13; CHECK-NEXT: ret 14 15define <8 x i16> @test_sllw_2(<8 x i16> %InVec) { 16entry: 17 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 18 ret <8 x i16> %shl 19} 20 21; CHECK-LABEL: test_sllw_2: 22; CHECK: paddw %xmm0, %xmm0 23; CHECK-NEXT: ret 24 25define <8 x i16> @test_sllw_3(<8 x i16> %InVec) { 26entry: 27 %shl = shl <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> 28 ret <8 x i16> %shl 29} 30 31; CHECK-LABEL: test_sllw_3: 32; CHECK: xorps %xmm0, %xmm0 33; CHECK-NEXT: ret 34 35define <4 x i32> @test_slld_1(<4 x i32> %InVec) { 36entry: 37 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0> 38 ret <4 x i32> %shl 39} 40 41; CHECK-LABEL: test_slld_1: 42; CHECK: pslld $0, %xmm0 43; CHECK-NEXT: ret 44 45define <4 x i32> @test_slld_2(<4 x i32> %InVec) { 46entry: 47 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1> 48 ret <4 x i32> %shl 49} 50 51; CHECK-LABEL: test_slld_2: 52; CHECK: paddd %xmm0, %xmm0 53; CHECK-NEXT: ret 54 55define <4 x i32> @test_slld_3(<4 x i32> %InVec) { 56entry: 57 %shl = shl <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32> 58 ret <4 x i32> %shl 59} 60 61; CHECK-LABEL: test_slld_3: 62; CHECK: xorps %xmm0, %xmm0 63; CHECK-NEXT: ret 64 65define <2 x i64> @test_sllq_1(<2 x i64> %InVec) { 66entry: 67 %shl = shl <2 x i64> %InVec, <i64 0, i64 0> 68 ret <2 x i64> %shl 69} 70 71; CHECK-LABEL: test_sllq_1: 72; CHECK: psllq $0, %xmm0 73; CHECK-NEXT: ret 74 75define <2 x i64> @test_sllq_2(<2 x i64> %InVec) { 76entry: 77 %shl = shl <2 x i64> %InVec, <i64 1, i64 1> 78 ret <2 x i64> %shl 79} 80 81; CHECK-LABEL: test_sllq_2: 82; CHECK: paddq %xmm0, %xmm0 83; CHECK-NEXT: ret 84 85define <2 x i64> @test_sllq_3(<2 x i64> %InVec) { 86entry: 87 %shl = shl <2 x i64> %InVec, <i64 64, i64 64> 88 ret <2 x i64> %shl 89} 90 91; CHECK-LABEL: test_sllq_3: 92; CHECK: xorps %xmm0, %xmm0 93; CHECK-NEXT: ret 94 95; SSE2 Arithmetic Shift 96 97define <8 x i16> @test_sraw_1(<8 x i16> %InVec) { 98entry: 99 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 100 ret <8 x i16> %shl 101} 102 103; CHECK-LABEL: test_sraw_1: 104; CHECK: psraw $0, %xmm0 105; CHECK-NEXT: ret 106 107define <8 x i16> @test_sraw_2(<8 x i16> %InVec) { 108entry: 109 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 110 ret <8 x i16> %shl 111} 112 113; CHECK-LABEL: test_sraw_2: 114; CHECK: psraw $1, %xmm0 115; CHECK-NEXT: ret 116 117define <8 x i16> @test_sraw_3(<8 x i16> %InVec) { 118entry: 119 %shl = ashr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> 120 ret <8 x i16> %shl 121} 122 123; CHECK-LABEL: test_sraw_3: 124; CHECK: psraw $16, %xmm0 125; CHECK-NEXT: ret 126 127define <4 x i32> @test_srad_1(<4 x i32> %InVec) { 128entry: 129 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0> 130 ret <4 x i32> %shl 131} 132 133; CHECK-LABEL: test_srad_1: 134; CHECK: psrad $0, %xmm0 135; CHECK-NEXT: ret 136 137define <4 x i32> @test_srad_2(<4 x i32> %InVec) { 138entry: 139 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1> 140 ret <4 x i32> %shl 141} 142 143; CHECK-LABEL: test_srad_2: 144; CHECK: psrad $1, %xmm0 145; CHECK-NEXT: ret 146 147define <4 x i32> @test_srad_3(<4 x i32> %InVec) { 148entry: 149 %shl = ashr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32> 150 ret <4 x i32> %shl 151} 152 153; CHECK-LABEL: test_srad_3: 154; CHECK: psrad $32, %xmm0 155; CHECK-NEXT: ret 156 157; SSE Logical Shift Right 158 159define <8 x i16> @test_srlw_1(<8 x i16> %InVec) { 160entry: 161 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 162 ret <8 x i16> %shl 163} 164 165; CHECK-LABEL: test_srlw_1: 166; CHECK: psrlw $0, %xmm0 167; CHECK-NEXT: ret 168 169define <8 x i16> @test_srlw_2(<8 x i16> %InVec) { 170entry: 171 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 172 ret <8 x i16> %shl 173} 174 175; CHECK-LABEL: test_srlw_2: 176; CHECK: psrlw $1, %xmm0 177; CHECK-NEXT: ret 178 179define <8 x i16> @test_srlw_3(<8 x i16> %InVec) { 180entry: 181 %shl = lshr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> 182 ret <8 x i16> %shl 183} 184 185; CHECK-LABEL: test_srlw_3: 186; CHECK: xorps %xmm0, %xmm0 187; CHECK-NEXT: ret 188 189define <4 x i32> @test_srld_1(<4 x i32> %InVec) { 190entry: 191 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0> 192 ret <4 x i32> %shl 193} 194 195; CHECK-LABEL: test_srld_1: 196; CHECK: psrld $0, %xmm0 197; CHECK-NEXT: ret 198 199define <4 x i32> @test_srld_2(<4 x i32> %InVec) { 200entry: 201 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1> 202 ret <4 x i32> %shl 203} 204 205; CHECK-LABEL: test_srld_2: 206; CHECK: psrld $1, %xmm0 207; CHECK-NEXT: ret 208 209define <4 x i32> @test_srld_3(<4 x i32> %InVec) { 210entry: 211 %shl = lshr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32> 212 ret <4 x i32> %shl 213} 214 215; CHECK-LABEL: test_srld_3: 216; CHECK: xorps %xmm0, %xmm0 217; CHECK-NEXT: ret 218 219define <2 x i64> @test_srlq_1(<2 x i64> %InVec) { 220entry: 221 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0> 222 ret <2 x i64> %shl 223} 224 225; CHECK-LABEL: test_srlq_1: 226; CHECK: psrlq $0, %xmm0 227; CHECK-NEXT: ret 228 229define <2 x i64> @test_srlq_2(<2 x i64> %InVec) { 230entry: 231 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1> 232 ret <2 x i64> %shl 233} 234 235; CHECK-LABEL: test_srlq_2: 236; CHECK: psrlq $1, %xmm0 237; CHECK-NEXT: ret 238 239define <2 x i64> @test_srlq_3(<2 x i64> %InVec) { 240entry: 241 %shl = lshr <2 x i64> %InVec, <i64 64, i64 64> 242 ret <2 x i64> %shl 243} 244 245; CHECK-LABEL: test_srlq_3: 246; CHECK: xorps %xmm0, %xmm0 247; CHECK-NEXT: ret 248