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1 // events from file arm/armv7-common/events
2     {0x00, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PMNC_SW_INCR",
3      "Software increment of PMNC registers"},
4     {0x01, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "IFETCH_MISS",
5      "Instruction fetch misses from cache or normal cacheable memory"},
6     {0x02, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "ITLB_MISS",
7      "Instruction fetch misses from TLB"},
8     {0x03, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DCACHE_REFILL",
9      "Data R/W operation that causes a refill from cache or normal cacheable memory"},
10     {0x04, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DCACHE_ACCESS",
11      "Data R/W from cache"},
12     {0x05, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DTLB_REFILL",
13      "Data R/W that causes a TLB refill"},
14     {0x06, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DREAD",
15      "Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code)"},
16     {0x07, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DWRITE",
17      "Data write architecturally executed"},
18     {0x08, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "INSTR_EXECUTED",
19      "All executed instructions"},
20     {0x09, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "EXC_TAKEN",
21      "Exception taken"},
22     {0x0A, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "EXC_EXECUTED",
23      "Exception return architecturally executed"},
24     {0x0B, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "CID_WRITE",
25      "Instruction that writes to the Context ID Register architecturally executed"},
26     {0x0C, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_WRITE",
27      "SW change of PC, architecturally executed (not by exceptions)"},
28     {0x0D, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_IMM_BRANCH",
29      "Immediate branch instruction executed (taken or not)"},
30     {0x0E, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_PROC_RETURN",
31      "Procedure return architecturally executed (not by exceptions)"},
32     {0x0F, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "UNALIGNED_ACCESS",
33      "Unaligned access architecturally executed"},
34     {0x10, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_BRANCH_MIS_PRED",
35      "Branch mispredicted or not predicted. Counts pipeline flushes because of misprediction"},
36     {0x12, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_BRANCH_MIS_USED",
37      "Branch or change in program flow that could have been predicted"},
38     {0xFF, CTR(0), 0, "CPU_CYCLES",
39      "Number of CPU cycles"},
40 // events from file arm/armv7/events
41     {0x40, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "WRITE_BUFFER_FULL",
42      "Any write buffer full cycle"},
43     {0x41, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_STORE_MERGED",
44      "Any store that is merged in L2 cache"},
45     {0x42, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_STORE_BUFF",
46      "Any bufferable store from load/store to L2 cache"},
47     {0x43, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_ACCESS",
48      "Any access to L2 cache"},
49     {0x44, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_CACH_MISS",
50      "Any cacheable miss in L2 cache"},
51     {0x45, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "AXI_READ_CYCLES",
52      "Number of cycles for an active AXI read"},
53     {0x46, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "AXI_WRITE_CYCLES",
54      "Number of cycles for an active AXI write"},
55     {0x47, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "MEMORY_REPLAY",
56      "Any replay event in the memory subsystem"},
57     {0x48, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "UNALIGNED_ACCESS_REPLAY",
58      "Unaligned access that causes a replay"},
59     {0x49, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_DATA_MISS",
60      "L1 data cache miss as a result of the hashing algorithm"},
61     {0x4A, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_INST_MISS",
62      "L1 instruction cache miss as a result of the hashing algorithm"},
63     {0x4B, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_DATA_COLORING",
64      "L1 data access in which a page coloring alias occurs"},
65     {0x4C, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_NEON_DATA",
66      "NEON data access that hits L1 cache"},
67     {0x4D, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_NEON_CACH_DATA",
68      "NEON cacheable data access that hits L1 cache"},
69     {0x4E, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_NEON",
70      "L2 access as a result of NEON memory access"},
71     {0x4F, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_NEON_HIT",
72      "Any NEON hit in L2 cache"},
73     {0x50, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_INST",
74      "Any L1 instruction cache access, excluding CP15 cache accesses"},
75     {0x51, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_RETURN_MIS_PRED",
76      "Return stack misprediction at return stack pop (incorrect target address)"},
77     {0x52, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_BRANCH_FAILED",
78      "Branch prediction misprediction"},
79     {0x53, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_BRANCH_TAKEN",
80      "Any predicted branch that is taken"},
81     {0x54, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_BRANCH_EXECUTED",
82      "Any taken branch that is executed"},
83     {0x55, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "OP_EXECUTED",
84      "Number of operations executed (in instruction or mutli-cycle instruction)"},
85     {0x56, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_INST_STALL",
86      "Cycles where no instruction available"},
87     {0x57, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_INST",
88      "Number of instructions issued in a cycle"},
89     {0x58, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_NEON_DATA_STALL",
90      "Number of cycles the processor waits on MRC data from NEON"},
91     {0x59, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_NEON_INST_STALL",
92      "Number of cycles the processor waits on NEON instruction queue or NEON load queue"},
93     {0x5A, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "NEON_CYCLES",
94      "Number of cycles NEON and integer processors are not idle"},
95     {0x70, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PMU0_EVENTS",
96      "Number of events from external input source PMUEXTIN[0]"},
97     {0x71, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PMU1_EVENTS",
98      "Number of events from external input source PMUEXTIN[1]"},
99     {0x72, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PMU_EVENTS",
100      "Number of events from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"},
101