1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are
4 // met:
5 //
6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided
11 // with the distribution.
12 // * Neither the name of Google Inc. nor the names of its
13 // contributors may be used to endorse or promote products derived
14 // from this software without specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28 // CPU specific code for arm independent of OS goes here.
29
30 #include <sys/syscall.h>
31 #include <unistd.h>
32
33 #ifdef __mips
34 #include <asm/cachectl.h>
35 #endif // #ifdef __mips
36
37 #include "v8.h"
38
39 #if defined(V8_TARGET_ARCH_MIPS)
40
41 #include "cpu.h"
42 #include "macro-assembler.h"
43
44 #include "simulator.h" // For cache flushing.
45
46 namespace v8 {
47 namespace internal {
48
49
SetUp()50 void CPU::SetUp() {
51 CpuFeatures::Probe();
52 }
53
54
SupportsCrankshaft()55 bool CPU::SupportsCrankshaft() {
56 return CpuFeatures::IsSupported(FPU);
57 }
58
59
FlushICache(void * start,size_t size)60 void CPU::FlushICache(void* start, size_t size) {
61 // Nothing to do, flushing no instructions.
62 if (size == 0) {
63 return;
64 }
65
66 #if !defined (USE_SIMULATOR)
67 #if defined(ANDROID)
68 // Workaround for a deserializer bug. Bionic usermode cacheflush
69 // fails in deserializer for a size of Page::kPageSize (1MB),
70 // because that region contains protected pages. Switch to kernel
71 // cacheflush in this case.
72 if (size >= static_cast<size_t>(Page::kPageSize)) {
73 int res;
74 // See http://www.linux-mips.org/wiki/Cacheflush_Syscall.
75 res = syscall(__NR_cacheflush, start, size, ICACHE);
76 if (res) {
77 V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache");
78 }
79 } else {
80 // Bionic cacheflush can typically run in userland, avoiding kernel call.
81 char *end = reinterpret_cast<char *>(start) + size;
82 cacheflush(
83 reinterpret_cast<intptr_t>(start), reinterpret_cast<intptr_t>(end), 0);
84 }
85 #else // ANDROID
86 int res;
87 // See http://www.linux-mips.org/wiki/Cacheflush_Syscall.
88 res = syscall(__NR_cacheflush, start, size, ICACHE);
89 if (res) {
90 V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache");
91 }
92 #endif // ANDROID
93 #else // USE_SIMULATOR.
94 // Not generating mips instructions for C-code. This means that we are
95 // building a mips emulator based target. We should notify the simulator
96 // that the Icache was flushed.
97 // None of this code ends up in the snapshot so there are no issues
98 // around whether or not to generate the code when building snapshots.
99 Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
100 #endif // USE_SIMULATOR.
101 }
102
103
DebugBreak()104 void CPU::DebugBreak() {
105 #ifdef __mips
106 asm volatile("break");
107 #endif // #ifdef __mips
108 }
109
110
111 } } // namespace v8::internal
112
113 #endif // V8_TARGET_ARCH_MIPS
114