Searched refs:LR (Results 1 – 14 of 14) sorted by relevance
| /art/runtime/arch/arm/ |
| D | quick_method_frame_info_arm.h | 47 (type == Runtime::kSaveAll ? kArmCalleeSaveAllSpills : 0) | (1 << art::arm::LR); in ArmCalleeSaveCoreSpills()
79 POPCOUNT(ArmCalleeSaveCoreSpills(type) & (-(1 << LR))) * kArmPointerSize; in ArmCalleeSaveLrOffset()
|
| D | registers_arm.h | 47 LR = 14, enumerator
|
| D | quick_entrypoints_arm.S | 346 ldr r14, [r0, #56] @ (LR from gprs_ 56=4*14)
1113 str lr, [sp, #-16]! @ expand the frame and pass LR
1119 blx artInstrumentationMethodEntryFromCode @ (Method*, Object*, Thread*, SP, LR)
|
| /art/runtime/arch/arm64/ |
| D | quick_method_frame_info_arm64.h | 33 (1 << art::arm64::LR);
99 POPCOUNT(Arm64CalleeSaveCoreSpills(type) & (-(1 << LR))) * kArm64PointerSize; in Arm64CalleeSaveLrOffset()
|
| D | context_arm64.cc | 41 gprs_[LR] = &pc_; in Reset()
44 pc_ = Arm64Context::kBadGprBase + LR; in Reset()
|
| D | context_arm64.h | 45 bool success = SetGPR(LR, new_lr); in SetPC()
|
| D | registers_arm64.h | 64 LR = 30, enumerator
|
| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 69 __ ldr(LR, Address(TR, offset)); in EmitNativeCode()
70 __ blx(LR); in EmitNativeCode()
107 __ ldr(LR, Address(TR, offset)); in EmitNativeCode()
108 __ blx(LR); in EmitNativeCode()
236 blocked_registers[LR] = true; in SetupBlockedRegisters()
284 core_spill_mask_ |= (1 << LR | 1 << R6 | 1 << R7); in GenerateFrameEntry()
285 __ PushList(1 << LR | 1 << R6 | 1 << R7); in GenerateFrameEntry()
857 __ ldr(LR, Address(temp, in VisitInvokeStatic()
860 __ blx(LR); in VisitInvokeStatic()
1003 __ ldr(LR, Address(TR, offset)); in VisitNewInstance()
[all …]
|
| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 136 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR; in CoreSpillMask()
|
| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 182 1 << X26 | 1 << X27 | 1 << X28 | 1 << X29 | 1 << LR; in CoreSpillMask()
|
| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 787 __ ldm(DB_W, R4, (1 << LR | 1 << R11)); in TEST()
788 __ ldm(DB, R4, (1 << LR | 1 << R11)); in TEST()
808 __ stm(IA_W, R4, (1 << LR | 1 << R11)); in TEST()
809 __ stm(IA, R4, (1 << LR | 1 << R11)); in TEST()
1087 __ blx(LR); in TEST()
1088 __ bx(LR); in TEST()
|
| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 659 StoreToOffset(LR, SP, reg_offset); in BuildFrame()
730 LoadFromOffset(LR, SP, reg_offset); in RemoveFrame()
|
| D | managed_register_arm64_test.cc | 653 EXPECT_TRUE(vixl::lr.Is(Arm64Assembler::reg_x(LR))); in TEST()
|
| /art/compiler/utils/arm/ |
| D | assembler_arm.cc | 402 RegList push_list = 1 << LR; in BuildFrame()
|