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Searched refs:BaseOffs (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp1048 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && in operator ==()
1070 if (BaseOffs) { in print()
1072 << BaseOffs; in print()
1613 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; in MatchScaledValue()
2080 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
2086 AddrMode.BaseOffs -= ConstantOffset; in MatchOperationAddr()
2095 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
2120 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
2192 AddrMode.BaseOffs += CI->getSExtValue(); in MatchAddr()
2195 AddrMode.BaseOffs -= CI->getSExtValue(); in MatchAddr()
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DBasicTargetTransformInfo.cpp153 AM.BaseOffs = BaseOffset; in isLegalAddressingMode()
164 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
DTargetLoweringBase.cpp1434 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1446 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1451 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Analysis/
DBasicAliasAnalysis.cpp290 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, in DecomposeGEPExpression() argument
297 BaseOffs = 0; in DecomposeGEPExpression()
358 BaseOffs += DL->getStructLayout(STy)->getElementOffset(FieldNo); in DecomposeGEPExpression()
365 BaseOffs += DL->getTypeAllocSize(*GTI)*CIdx->getSExtValue(); in DecomposeGEPExpression()
385 BaseOffs += IndexOffset.getSExtValue()*Scale; in DecomposeGEPExpression()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1913 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1919 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1926 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1929 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1934 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1937 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1941 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1944 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/external/llvm/include/llvm/Target/
DTargetLowering.h1251 int64_t BaseOffs; member
1254 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1634 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { in isLegalAddressingMode()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp8749 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
8761 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
8766 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp2570 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale) in isLegalAddressingMode()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp361 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp6200 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
6214 int64_t Offset = AM.BaseOffs; in isLegalAddressingMode()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp9934 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
9950 if (AM.BaseOffs) in isLegalAddressingMode()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp7561 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
7569 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp16653 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
16671 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()