| /external/clang/test/Sema/ |
| D | deref.c | 37 typedef const void CVT; typedef
38 extern CVT cv3;
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| /external/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 147 EVT CVT = Count.getValueType(); in EmitTargetCodeForMemset() local
148 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, in EmitTargetCodeForMemset()
149 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); in EmitTargetCodeForMemset()
150 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
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| D | X86ISelLowering.cpp | 5834 EVT CVT = Ld.getValueType(); in LowerVectorBroadcast() local
5835 assert(!CVT.isVector() && "Must not broadcast a vector type"); in LowerVectorBroadcast()
5836 unsigned ScalarSize = CVT.getSizeInBits(); in LowerVectorBroadcast()
5850 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, in LowerVectorBroadcast()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcher.cpp | 441 if (const CheckValueTypeMatcher *CVT = dyn_cast<CheckValueTypeMatcher>(M)) in isContradictoryImpl() local
442 return CVT->getTypeName() != getTypeName(); in isContradictoryImpl()
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| /external/chromium_org/third_party/ots/src/ |
| D | ots.h | 188 F(cvt, CVT) \
|
| /external/valgrind/main/VEX/priv/ |
| D | guest_amd64_toIR.c | 10425 # define CVT(_t) binop( Iop_F64toF32, mkexpr(rmode), mkexpr(_t) ) in dis_CVTPD2PS_128() macro
10428 putXMMRegLane32F( rG, 1, CVT(t1) ); in dis_CVTPD2PS_128()
10429 putXMMRegLane32F( rG, 0, CVT(t0) ); in dis_CVTPD2PS_128()
10430 # undef CVT in dis_CVTPD2PS_128()
10470 # define CVT(_t) \ in dis_CVTxPS2DQ_128() macro
10476 putXMMRegLane32( rG, 3, CVT(t3) ); in dis_CVTxPS2DQ_128()
10477 putXMMRegLane32( rG, 2, CVT(t2) ); in dis_CVTxPS2DQ_128()
10478 putXMMRegLane32( rG, 1, CVT(t1) ); in dis_CVTxPS2DQ_128()
10479 putXMMRegLane32( rG, 0, CVT(t0) ); in dis_CVTxPS2DQ_128()
10480 # undef CVT in dis_CVTxPS2DQ_128()
[all …]
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| D | guest_x86_toIR.c | 9670 # define CVT(_t) binop( Iop_F64toF32, \ in disInstr_X86_WRK() macro
9674 putXMMRegLane32F( gregOfRM(modrm), 3, CVT(t3) ); in disInstr_X86_WRK()
9675 putXMMRegLane32F( gregOfRM(modrm), 2, CVT(t2) ); in disInstr_X86_WRK()
9676 putXMMRegLane32F( gregOfRM(modrm), 1, CVT(t1) ); in disInstr_X86_WRK()
9677 putXMMRegLane32F( gregOfRM(modrm), 0, CVT(t0) ); in disInstr_X86_WRK()
9679 # undef CVT in disInstr_X86_WRK()
9713 # define CVT(_t) binop( Iop_F64toI32S, \ in disInstr_X86_WRK() macro
9719 putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); in disInstr_X86_WRK()
9720 putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); in disInstr_X86_WRK()
9722 # undef CVT in disInstr_X86_WRK()
[all …]
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 469 NV50_IR_OPCODE_CASE(ROUND, CVT); in translateOpcode()
504 NV50_IR_OPCODE_CASE(I2F, CVT); in translateOpcode()
522 NV50_IR_OPCODE_CASE(F2I, CVT); in translateOpcode()
531 NV50_IR_OPCODE_CASE(F2U, CVT); in translateOpcode()
532 NV50_IR_OPCODE_CASE(U2F, CVT); in translateOpcode()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 469 NV50_IR_OPCODE_CASE(ROUND, CVT); in translateOpcode()
504 NV50_IR_OPCODE_CASE(I2F, CVT); in translateOpcode()
522 NV50_IR_OPCODE_CASE(F2I, CVT); in translateOpcode()
531 NV50_IR_OPCODE_CASE(F2U, CVT); in translateOpcode()
532 NV50_IR_OPCODE_CASE(U2F, CVT); in translateOpcode()
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| /external/chromium_org/third_party/brotli/src/ |
| D | README | 93 test uses a single stream. MTX also compresses the CVT table (an upper bound on
|
| /external/chromium_org/third_party/icu/source/data/zone/ |
| D | root.txt | 221 ss{"CVT"}
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| D | sv.txt | 520 sg{"CVT"}
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 35 // CVT conversion modes
|