| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 76 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
79 NewOpcode = Hexagon::JMP_f; in InvertAndChangeJumpTarget()
83 NewOpcode = Hexagon::JMP_t; in InvertAndChangeJumpTarget()
87 NewOpcode = Hexagon::JMP_fnew_t; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::JMP_tnew_t; in InvertAndChangeJumpTarget()
98 MI->setDesc(QII->get(NewOpcode)); in InvertAndChangeJumpTarget()
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| D | HexagonVLIWPacketizer.cpp | 439 int NewOpcode; in PromoteToDotNew() local
441 NewOpcode = QII->GetDotNewPredOp(MI, MBPI); in PromoteToDotNew()
443 NewOpcode = QII->GetDotNewOp(MI); in PromoteToDotNew()
444 MI->setDesc(QII->get(NewOpcode)); in PromoteToDotNew()
451 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); in DemoteToDotOld() local
452 MI->setDesc(QII->get(NewOpcode)); in DemoteToDotOld()
772 int NewOpcode = QII->GetDotNewOp(MI); in CanPromoteToDotNew() local
773 const MCInstrDesc &desc = QII->get(NewOpcode); in CanPromoteToDotNew()
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| D | HexagonInstrInfo.cpp | 1585 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in GetDotNewPredOp() local
1586 if (NewOpcode >= 0) // Valid predicate new instruction in GetDotNewPredOp()
1587 return NewOpcode; in GetDotNewPredOp()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 137 int NewOpcode; in InsertSPImmInst() local
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
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| /external/llvm/lib/Target/R600/ |
| D | AMDILCFGStructurizer.cpp | 228 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
230 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
232 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
233 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
236 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
238 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
469 int NewOpcode, DebugLoc DL) { in insertInstrEnd() argument
471 ->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
478 int NewOpcode, DebugLoc DL) { in insertInstrBefore() argument
480 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
[all …]
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| D | SIISelLowering.cpp | 1671 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); in AdjustInstrPostInstrSelection() local
1672 MI->setDesc(TII->get(NewOpcode)); in AdjustInstrPostInstrSelection()
1681 unsigned NewOpcode = N->getMachineOpcode(); in AdjustRegClass() local
1686 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64; in AdjustRegClass()
1689 if (NewOpcode == N->getMachineOpcode()) { in AdjustRegClass()
1690 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64; in AdjustRegClass()
1695 if (NewOpcode == N->getMachineOpcode()) { in AdjustRegClass()
1696 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64; in AdjustRegClass()
1708 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops); in AdjustRegClass()
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| D | SIInstrInfo.cpp | 1116 unsigned NewOpcode = getVALUOp(*MI); in moveSMRDToVALU() local
1162 MI->setDesc(get(NewOpcode)); in moveSMRDToVALU()
1183 unsigned NewOpcode = getVALUOp(*Inst); in moveToVALU() local
1247 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { in moveToVALU()
1255 const MCInstrDesc &NewDesc = get(NewOpcode); in moveToVALU()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 427 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
431 if (!NewOpcode) { in emitEpilogue()
436 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
437 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
440 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
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| D | SystemZInstrInfo.cpp | 51 unsigned NewOpcode) const { in splitMove()
73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
92 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
93 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
725 unsigned NewOpcode; in convertToThreeAddress() local
727 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
729 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
736 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode)) in convertToThreeAddress()
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| D | SystemZInstrInfo.h | 118 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); in EncodeInstruction() local
181 if (NewOpcode != -1) { in EncodeInstruction()
184 Opcode = NewOpcode; in EncodeInstruction()
185 TmpInst.setOpcode (NewOpcode); in EncodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 263 unsigned NewOpcode = 0; in SimplifyMOVSX() local
270 NewOpcode = X86::CBW; in SimplifyMOVSX()
274 NewOpcode = X86::CWDE; in SimplifyMOVSX()
278 NewOpcode = X86::CDQE; in SimplifyMOVSX()
282 if (NewOpcode != 0) { in SimplifyMOVSX()
284 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
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| D | X86InstrInfo.cpp | 3584 unsigned NewOpcode = 0; in optimizeCompareInstr() local
3607 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
3608 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
3609 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
3610 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
3611 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
3612 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
3613 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
3614 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; in optimizeCompareInstr()
3615 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; in optimizeCompareInstr()
[all …]
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 1350 std::string NewOpcode; in ParseInstruction() local
1353 NewOpcode = Name; in ParseInstruction()
1354 NewOpcode += '+'; in ParseInstruction()
1355 Name = NewOpcode; in ParseInstruction()
1359 NewOpcode = Name; in ParseInstruction()
1360 NewOpcode += '-'; in ParseInstruction()
1361 Name = NewOpcode; in ParseInstruction()
1367 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1375 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 669 unsigned NewOpcode = in EmitInstruction() local
673 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
683 unsigned NewOpcode = in EmitInstruction() local
689 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
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| D | PPCRegisterInfo.cpp | 821 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
822 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3773 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3777 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
3785 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3789 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
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