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Searched refs:RCX (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dabi-isel.ll58 ; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r..]]
59 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
87 ; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
88 ; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]])
94 ; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
95 ; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]])
101 ; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
102 ; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
130 ; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
131 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
[all …]
Dfp-stack-O0.ll11 ; CHECK-NEXT: movq %rsp, [[RCX:%r..]]
14 ; CHECK-NEXT: fstpt 16([[RCX]])
16 ; CHECK-NEXT: fstpt ([[RCX]])
Dor-address.ll50 ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
51 ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
52 ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
53 ; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
/external/llvm/test/MC/X86/
Dintel-syntax.s23 mov RCX, QWORD PTR [0]
27 mov BYTE PTR [RDX + RCX], DIL
29 movzx EDI, WORD PTR [RCX + 2]
451 xchg RAX, RCX
452 xchg RCX, RAX
/external/libunwind/src/x86_64/
Dinit.h51 c->dwarf.loc[RCX] = REG_INIT_LOC(c, rcx, RCX); in common_init()
Dunwind_i.h41 #define RCX 2 macro
DGos-freebsd.c113 c->dwarf.loc[RCX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RCX, 0); in unw_handle_signal_frame()
133 c->dwarf.loc[RCX] = c->dwarf.loc[R10]; in unw_handle_signal_frame()
DGregs.c107 case UNW_X86_64_RCX: loc = c->dwarf.loc[RCX]; break; in tdep_access_reg()
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h40 #define RCX 88 macro
/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp133 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
150 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
230 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : in EmitTargetCodeForMemcpy()
DX86CallingConv.td38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
231 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
307 // Do not pass the sret argument in RCX, the Win64 thiscall calling
308 // convention requires "this" to be passed in RCX.
313 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
319 [RCX , RDX , R8 , R9 ]>>,
349 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
545 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
548 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
624 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
[all …]
DX86RegisterInfo.cpp554 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
566 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
603 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
639 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
675 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
676 return X86::RCX; in getX86SubSuperRegister()
DX86RegisterInfo.td131 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
339 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
363 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
365 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
367 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
386 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
DX86InstrSystem.td21 let Defs = [RAX, RCX, RDX] in
467 let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in
482 let Defs = [RDX, RAX], Uses = [RCX] in
485 let Uses = [RDX, RAX, RCX] in
DX86InstrCompiler.td350 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
381 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
382 let Uses = [AL,RCX,RDI] in
386 let Uses = [AX,RCX,RDI] in
390 let Uses = [RAX,RCX,RDI] in
395 let Uses = [RAX,RCX,RDI] in
428 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
700 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
/external/lzma/Asm/x86/
D7zAsm.asm63 r1 equ RCX
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h172 ENTRY(RCX) \
190 ENTRY(RCX) \
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmInstrumentation.cpp358 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX)); in InstrumentMemOperandSmallImpl()
429 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RCX)); in InstrumentMemOperandSmallImpl()
DX86Operand.h344 case X86::RCX: return X86::ECX; in getGR32FromGR64()
/external/llvm/test/DebugInfo/X86/
Dop_deref.ll23 ; ASM-CHECK: DEBUG_VALUE: vla <- RCX
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c105 GENOFFSET(AMD64,amd64,RCX); in foo()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-amd64-linux.c359 SC2(rcx,RCX); in synth_ucontext()
/external/libunwind/src/ptrace/
D_UPT_reg_offset.c295 UNW_R_OFF(RCX, rcx)
/external/valgrind/main/memcheck/
Dmc_machine.c576 if (o == GOF(RCX) && is1248) return o; in get_otrack_shadow_offset_wrk()
619 if (o == 1+ GOF(RCX) && szB == 1) return GOF(DFLAG); in get_otrack_shadow_offset_wrk()
673 if (o == 4+ GOF(RCX) && sz == 4) return GOF(RCX); in get_otrack_shadow_offset_wrk()

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