| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitTFRCondSets.cpp | 100 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction() local
118 if (DestReg != SrcReg2) { in runOnMachineFunction()
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
157 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction() local
173 if (DestReg != SrcReg2) { in runOnMachineFunction()
176 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
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| D | HexagonInstrInfo.h | 75 unsigned &SrcReg, unsigned &SrcReg2,
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| D | HexagonInstrInfo.cpp | 343 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
397 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
407 SrcReg2 = 0; in analyzeCompare()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 382 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ? in fuseCompareAndBranch() local
387 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareAndBranch()
417 if (SrcReg2) in fuseCompareAndBranch()
418 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareAndBranch()
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| D | SystemZInstrInfo.h | 153 unsigned &SrcReg2, int &Mask, int &Value) const override;
155 unsigned SrcReg2, int Mask, int Value,
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| D | SystemZInstrInfo.cpp | 400 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
408 SrcReg2 = 0; in analyzeCompare()
484 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
487 assert(!SrcReg2 && "Only optimizing constant comparisons so far"); in optimizeCompareInstr()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 149 unsigned &SrcReg2, int &CmpMask,
154 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | AArch64FastISel.cpp | 952 unsigned SrcReg2; in EmitCmp() local
954 SrcReg2 = getRegForValue(Src2Value); in EmitCmp()
955 if (SrcReg2 == 0) in EmitCmp()
965 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in EmitCmp()
966 if (SrcReg2 == 0) in EmitCmp()
982 .addReg(SrcReg2); in EmitCmp()
990 .addReg(SrcReg2); in EmitCmp()
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| D | AArch64InstrInfo.cpp | 568 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
587 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
596 SrcReg2 = 0; in analyzeCompare()
605 SrcReg2 = 0; in analyzeCompare()
658 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
696 if (CmpValue != 0 || SrcReg2 != 0) in optimizeCompareInstr()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 219 unsigned &SrcReg, unsigned &SrcReg2,
223 unsigned SrcReg, unsigned SrcReg2,
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| D | PPCFastISel.cpp | 796 unsigned SrcReg2 = 0; in PPCEmitCmp() local
798 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
799 if (SrcReg2 == 0) in PPCEmitCmp()
811 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
813 SrcReg2 = ExtReg; in PPCEmitCmp()
819 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1179 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1180 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1184 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1187 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
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| D | PPCInstrInfo.cpp | 1282 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
1293 SrcReg2 = 0; in analyzeCompare()
1304 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
1310 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
1411 if (SrcReg2 != 0) in optimizeCompareInstr()
1450 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1451 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1497 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 417 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
419 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
421 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
425 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 428 unsigned &SrcReg2, int &CmpMask,
435 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | X86InstrInfo.cpp | 2251 unsigned SrcReg2; in convertToThreeAddress() local
2254 SrcReg2, isKill2, isUndef2, ImplicitOp2)) in convertToThreeAddress()
2264 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
2271 LV->replaceKillInstruction(SrcReg2, MI, NewMI); in convertToThreeAddress()
3354 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
3366 SrcReg2 = 0; in analyzeCompare()
3376 SrcReg2 = 0; in analyzeCompare()
3385 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
3397 SrcReg2 = 0; in analyzeCompare()
3406 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1438 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1440 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1441 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1450 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1459 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1777 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1778 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1782 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
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| D | ARMBaseInstrInfo.h | 189 unsigned &SrcReg2, int &CmpMask,
197 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | ARMBaseInstrInfo.cpp | 2141 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
2148 SrcReg2 = 0; in analyzeCompare()
2155 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
2162 SrcReg2 = 0; in analyzeCompare()
2225 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
2232 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2233 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2255 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
2293 if (SrcReg2 != 0) in optimizeCompareInstr()
2321 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 773 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
782 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2) in emit3() argument
95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2) in emit3() argument
95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
|