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1//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// InstrSchedModel annotations for out-of-order CPUs.
11//
12// These annotations are independent of the itinerary classes defined below.
13
14// Instructions with folded loads need to read the memory operand immediately,
15// but other register operands don't have to be read until the load is ready.
16// These operands are marked with ReadAfterLd.
17def ReadAfterLd : SchedRead;
18
19// Instructions with both a load and a store folded are modeled as a folded
20// load + WriteRMW.
21def WriteRMW : SchedWrite;
22
23// Most instructions can fold loads, so almost every SchedWrite comes in two
24// variants: With and without a folded load.
25// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
26// with a folded load.
27class X86FoldableSchedWrite : SchedWrite {
28  // The SchedWrite to use when a load is folded into the instruction.
29  SchedWrite Folded;
30}
31
32// Multiclass that produces a linked pair of SchedWrites.
33multiclass X86SchedWritePair {
34  // Register-Memory operation.
35  def Ld : SchedWrite;
36  // Register-Register operation.
37  def NAME : X86FoldableSchedWrite {
38    let Folded = !cast<SchedWrite>(NAME#"Ld");
39  }
40}
41
42// Arithmetic.
43defm WriteALU  : X86SchedWritePair; // Simple integer ALU op.
44defm WriteIMul : X86SchedWritePair; // Integer multiplication.
45def  WriteIMulH : SchedWrite;       // Integer multiplication, high part.
46defm WriteIDiv : X86SchedWritePair; // Integer division.
47def  WriteLEA  : SchedWrite;        // LEA instructions can't fold loads.
48
49// Integer shifts and rotates.
50defm WriteShift : X86SchedWritePair;
51
52// Loads, stores, and moves, not folded with other operations.
53def WriteLoad  : SchedWrite;
54def WriteStore : SchedWrite;
55def WriteMove  : SchedWrite;
56
57// Idioms that clear a register, like xorps %xmm0, %xmm0.
58// These can often bypass execution ports completely.
59def WriteZero : SchedWrite;
60
61// Branches don't produce values, so they have no latency, but they still
62// consume resources. Indirect branches can fold loads.
63defm WriteJump : X86SchedWritePair;
64
65// Floating point. This covers both scalar and vector operations.
66defm WriteFAdd  : X86SchedWritePair; // Floating point add/sub/compare.
67defm WriteFMul  : X86SchedWritePair; // Floating point multiplication.
68defm WriteFDiv  : X86SchedWritePair; // Floating point division.
69defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
70defm WriteFRcp  : X86SchedWritePair; // Floating point reciprocal.
71defm WriteFMA   : X86SchedWritePair; // Fused Multiply Add.
72defm WriteFShuffle  : X86SchedWritePair; // Floating point vector shuffles.
73defm WriteFBlend  : X86SchedWritePair; // Floating point vector blends.
74defm WriteFVarBlend  : X86SchedWritePair; // Fp vector variable blends.
75
76// FMA Scheduling helper class.
77class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
78
79// Vector integer operations.
80defm WriteVecALU   : X86SchedWritePair; // Vector integer ALU op, no logicals.
81defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
82defm WriteVecIMul  : X86SchedWritePair; // Vector integer multiply.
83defm WriteShuffle  : X86SchedWritePair; // Vector shuffles.
84defm WriteBlend  : X86SchedWritePair; // Vector blends.
85defm WriteVarBlend  : X86SchedWritePair; // Vector variable blends.
86defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
87
88// Vector bitwise operations.
89// These are often used on both floating point and integer vectors.
90defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
91
92// Conversion between integer and float.
93defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
94defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
95defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
96
97// Strings instructions.
98// Packed Compare Implicit Length Strings, Return Mask
99defm WritePCmpIStrM : X86SchedWritePair;
100// Packed Compare Explicit Length Strings, Return Mask
101defm WritePCmpEStrM : X86SchedWritePair;
102// Packed Compare Implicit Length Strings, Return Index
103defm WritePCmpIStrI : X86SchedWritePair;
104// Packed Compare Explicit Length Strings, Return Index
105defm WritePCmpEStrI : X86SchedWritePair;
106
107// AES instructions.
108defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption.
109defm WriteAESIMC : X86SchedWritePair; // InvMixColumn.
110defm WriteAESKeyGen : X86SchedWritePair; // Key Generation.
111
112// Carry-less multiplication instructions.
113defm WriteCLMul : X86SchedWritePair;
114
115// Catch-all for expensive system instructions.
116def WriteSystem : SchedWrite;
117
118// AVX2.
119defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
120defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
121defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts.
122
123// Old microcoded instructions that nobody use.
124def WriteMicrocoded : SchedWrite;
125
126// Fence instructions.
127def WriteFence : SchedWrite;
128
129// Nop, not very useful expect it provides a model for nops!
130def WriteNop : SchedWrite;
131
132//===----------------------------------------------------------------------===//
133// Instruction Itinerary classes used for X86
134def IIC_ALU_MEM     : InstrItinClass;
135def IIC_ALU_NONMEM  : InstrItinClass;
136def IIC_LEA         : InstrItinClass;
137def IIC_LEA_16      : InstrItinClass;
138def IIC_MUL8        : InstrItinClass;
139def IIC_MUL16_MEM   : InstrItinClass;
140def IIC_MUL16_REG   : InstrItinClass;
141def IIC_MUL32_MEM   : InstrItinClass;
142def IIC_MUL32_REG   : InstrItinClass;
143def IIC_MUL64       : InstrItinClass;
144// imul by al, ax, eax, tax
145def IIC_IMUL8       : InstrItinClass;
146def IIC_IMUL16_MEM  : InstrItinClass;
147def IIC_IMUL16_REG  : InstrItinClass;
148def IIC_IMUL32_MEM  : InstrItinClass;
149def IIC_IMUL32_REG  : InstrItinClass;
150def IIC_IMUL64      : InstrItinClass;
151// imul reg by reg|mem
152def IIC_IMUL16_RM   : InstrItinClass;
153def IIC_IMUL16_RR   : InstrItinClass;
154def IIC_IMUL32_RM   : InstrItinClass;
155def IIC_IMUL32_RR   : InstrItinClass;
156def IIC_IMUL64_RM   : InstrItinClass;
157def IIC_IMUL64_RR   : InstrItinClass;
158// imul reg = reg/mem * imm
159def IIC_IMUL16_RMI  : InstrItinClass;
160def IIC_IMUL16_RRI  : InstrItinClass;
161def IIC_IMUL32_RMI  : InstrItinClass;
162def IIC_IMUL32_RRI  : InstrItinClass;
163def IIC_IMUL64_RMI  : InstrItinClass;
164def IIC_IMUL64_RRI  : InstrItinClass;
165// div
166def IIC_DIV8_MEM    : InstrItinClass;
167def IIC_DIV8_REG    : InstrItinClass;
168def IIC_DIV16       : InstrItinClass;
169def IIC_DIV32       : InstrItinClass;
170def IIC_DIV64       : InstrItinClass;
171// idiv
172def IIC_IDIV8       : InstrItinClass;
173def IIC_IDIV16      : InstrItinClass;
174def IIC_IDIV32      : InstrItinClass;
175def IIC_IDIV64      : InstrItinClass;
176// neg/not/inc/dec
177def IIC_UNARY_REG   : InstrItinClass;
178def IIC_UNARY_MEM   : InstrItinClass;
179// add/sub/and/or/xor/sbc/cmp/test
180def IIC_BIN_MEM     : InstrItinClass;
181def IIC_BIN_NONMEM  : InstrItinClass;
182// adc/sbc
183def IIC_BIN_CARRY_MEM     : InstrItinClass;
184def IIC_BIN_CARRY_NONMEM  : InstrItinClass;
185// shift/rotate
186def IIC_SR          : InstrItinClass;
187// shift double
188def IIC_SHD16_REG_IM : InstrItinClass;
189def IIC_SHD16_REG_CL : InstrItinClass;
190def IIC_SHD16_MEM_IM : InstrItinClass;
191def IIC_SHD16_MEM_CL : InstrItinClass;
192def IIC_SHD32_REG_IM : InstrItinClass;
193def IIC_SHD32_REG_CL : InstrItinClass;
194def IIC_SHD32_MEM_IM : InstrItinClass;
195def IIC_SHD32_MEM_CL : InstrItinClass;
196def IIC_SHD64_REG_IM : InstrItinClass;
197def IIC_SHD64_REG_CL : InstrItinClass;
198def IIC_SHD64_MEM_IM : InstrItinClass;
199def IIC_SHD64_MEM_CL : InstrItinClass;
200// cmov
201def IIC_CMOV16_RM : InstrItinClass;
202def IIC_CMOV16_RR : InstrItinClass;
203def IIC_CMOV32_RM : InstrItinClass;
204def IIC_CMOV32_RR : InstrItinClass;
205def IIC_CMOV64_RM : InstrItinClass;
206def IIC_CMOV64_RR : InstrItinClass;
207// set
208def IIC_SET_R : InstrItinClass;
209def IIC_SET_M : InstrItinClass;
210// jmp/jcc/jcxz
211def IIC_Jcc : InstrItinClass;
212def IIC_JCXZ : InstrItinClass;
213def IIC_JMP_REL : InstrItinClass;
214def IIC_JMP_REG : InstrItinClass;
215def IIC_JMP_MEM : InstrItinClass;
216def IIC_JMP_FAR_MEM : InstrItinClass;
217def IIC_JMP_FAR_PTR : InstrItinClass;
218// loop
219def IIC_LOOP : InstrItinClass;
220def IIC_LOOPE : InstrItinClass;
221def IIC_LOOPNE : InstrItinClass;
222// call
223def IIC_CALL_RI : InstrItinClass;
224def IIC_CALL_MEM : InstrItinClass;
225def IIC_CALL_FAR_MEM : InstrItinClass;
226def IIC_CALL_FAR_PTR : InstrItinClass;
227// ret
228def IIC_RET : InstrItinClass;
229def IIC_RET_IMM : InstrItinClass;
230//sign extension movs
231def IIC_MOVSX : InstrItinClass;
232def IIC_MOVSX_R16_R8 : InstrItinClass;
233def IIC_MOVSX_R16_M8 : InstrItinClass;
234def IIC_MOVSX_R16_R16 : InstrItinClass;
235def IIC_MOVSX_R32_R32 : InstrItinClass;
236//zero extension movs
237def IIC_MOVZX : InstrItinClass;
238def IIC_MOVZX_R16_R8 : InstrItinClass;
239def IIC_MOVZX_R16_M8 : InstrItinClass;
240
241def IIC_REP_MOVS : InstrItinClass;
242def IIC_REP_STOS : InstrItinClass;
243
244// SSE scalar/parallel binary operations
245def IIC_SSE_ALU_F32S_RR : InstrItinClass;
246def IIC_SSE_ALU_F32S_RM : InstrItinClass;
247def IIC_SSE_ALU_F64S_RR : InstrItinClass;
248def IIC_SSE_ALU_F64S_RM : InstrItinClass;
249def IIC_SSE_MUL_F32S_RR : InstrItinClass;
250def IIC_SSE_MUL_F32S_RM : InstrItinClass;
251def IIC_SSE_MUL_F64S_RR : InstrItinClass;
252def IIC_SSE_MUL_F64S_RM : InstrItinClass;
253def IIC_SSE_DIV_F32S_RR : InstrItinClass;
254def IIC_SSE_DIV_F32S_RM : InstrItinClass;
255def IIC_SSE_DIV_F64S_RR : InstrItinClass;
256def IIC_SSE_DIV_F64S_RM : InstrItinClass;
257def IIC_SSE_ALU_F32P_RR : InstrItinClass;
258def IIC_SSE_ALU_F32P_RM : InstrItinClass;
259def IIC_SSE_ALU_F64P_RR : InstrItinClass;
260def IIC_SSE_ALU_F64P_RM : InstrItinClass;
261def IIC_SSE_MUL_F32P_RR : InstrItinClass;
262def IIC_SSE_MUL_F32P_RM : InstrItinClass;
263def IIC_SSE_MUL_F64P_RR : InstrItinClass;
264def IIC_SSE_MUL_F64P_RM : InstrItinClass;
265def IIC_SSE_DIV_F32P_RR : InstrItinClass;
266def IIC_SSE_DIV_F32P_RM : InstrItinClass;
267def IIC_SSE_DIV_F64P_RR : InstrItinClass;
268def IIC_SSE_DIV_F64P_RM : InstrItinClass;
269
270def IIC_SSE_COMIS_RR : InstrItinClass;
271def IIC_SSE_COMIS_RM : InstrItinClass;
272
273def IIC_SSE_HADDSUB_RR : InstrItinClass;
274def IIC_SSE_HADDSUB_RM : InstrItinClass;
275
276def IIC_SSE_BIT_P_RR  : InstrItinClass;
277def IIC_SSE_BIT_P_RM  : InstrItinClass;
278
279def IIC_SSE_INTALU_P_RR  : InstrItinClass;
280def IIC_SSE_INTALU_P_RM  : InstrItinClass;
281def IIC_SSE_INTALUQ_P_RR  : InstrItinClass;
282def IIC_SSE_INTALUQ_P_RM  : InstrItinClass;
283
284def IIC_SSE_INTMUL_P_RR : InstrItinClass;
285def IIC_SSE_INTMUL_P_RM : InstrItinClass;
286
287def IIC_SSE_INTSH_P_RR : InstrItinClass;
288def IIC_SSE_INTSH_P_RM : InstrItinClass;
289def IIC_SSE_INTSH_P_RI : InstrItinClass;
290
291def IIC_SSE_INTSHDQ_P_RI : InstrItinClass;
292
293def IIC_SSE_SHUFP : InstrItinClass;
294def IIC_SSE_PSHUF_RI : InstrItinClass;
295def IIC_SSE_PSHUF_MI : InstrItinClass;
296
297def IIC_SSE_UNPCK : InstrItinClass;
298
299def IIC_SSE_MOVMSK : InstrItinClass;
300def IIC_SSE_MASKMOV : InstrItinClass;
301
302def IIC_SSE_PEXTRW : InstrItinClass;
303def IIC_SSE_PINSRW : InstrItinClass;
304
305def IIC_SSE_PABS_RR : InstrItinClass;
306def IIC_SSE_PABS_RM : InstrItinClass;
307
308def IIC_SSE_SQRTPS_RR : InstrItinClass;
309def IIC_SSE_SQRTPS_RM : InstrItinClass;
310def IIC_SSE_SQRTSS_RR : InstrItinClass;
311def IIC_SSE_SQRTSS_RM : InstrItinClass;
312def IIC_SSE_SQRTPD_RR : InstrItinClass;
313def IIC_SSE_SQRTPD_RM : InstrItinClass;
314def IIC_SSE_SQRTSD_RR : InstrItinClass;
315def IIC_SSE_SQRTSD_RM : InstrItinClass;
316
317def IIC_SSE_RCPP_RR : InstrItinClass;
318def IIC_SSE_RCPP_RM : InstrItinClass;
319def IIC_SSE_RCPS_RR : InstrItinClass;
320def IIC_SSE_RCPS_RM : InstrItinClass;
321
322def IIC_SSE_MOV_S_RR : InstrItinClass;
323def IIC_SSE_MOV_S_RM : InstrItinClass;
324def IIC_SSE_MOV_S_MR : InstrItinClass;
325
326def IIC_SSE_MOVA_P_RR : InstrItinClass;
327def IIC_SSE_MOVA_P_RM : InstrItinClass;
328def IIC_SSE_MOVA_P_MR : InstrItinClass;
329
330def IIC_SSE_MOVU_P_RR : InstrItinClass;
331def IIC_SSE_MOVU_P_RM : InstrItinClass;
332def IIC_SSE_MOVU_P_MR : InstrItinClass;
333
334def IIC_SSE_MOVDQ : InstrItinClass;
335def IIC_SSE_MOVD_ToGP : InstrItinClass;
336def IIC_SSE_MOVQ_RR : InstrItinClass;
337
338def IIC_SSE_MOV_LH : InstrItinClass;
339
340def IIC_SSE_LDDQU : InstrItinClass;
341
342def IIC_SSE_MOVNT : InstrItinClass;
343
344def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
345def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
346def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
347def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
348def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
349def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
350def IIC_SSE_PSHUFB_RR : InstrItinClass;
351def IIC_SSE_PSHUFB_RM : InstrItinClass;
352def IIC_SSE_PSIGN_RR : InstrItinClass;
353def IIC_SSE_PSIGN_RM : InstrItinClass;
354
355def IIC_SSE_PMADD : InstrItinClass;
356def IIC_SSE_PMULHRSW : InstrItinClass;
357def IIC_SSE_PALIGNRR : InstrItinClass;
358def IIC_SSE_PALIGNRM : InstrItinClass;
359def IIC_SSE_MWAIT : InstrItinClass;
360def IIC_SSE_MONITOR : InstrItinClass;
361
362def IIC_SSE_PREFETCH : InstrItinClass;
363def IIC_SSE_PAUSE : InstrItinClass;
364def IIC_SSE_LFENCE : InstrItinClass;
365def IIC_SSE_MFENCE : InstrItinClass;
366def IIC_SSE_SFENCE : InstrItinClass;
367def IIC_SSE_LDMXCSR : InstrItinClass;
368def IIC_SSE_STMXCSR : InstrItinClass;
369
370def IIC_SSE_CVT_PD_RR : InstrItinClass;
371def IIC_SSE_CVT_PD_RM : InstrItinClass;
372def IIC_SSE_CVT_PS_RR : InstrItinClass;
373def IIC_SSE_CVT_PS_RM : InstrItinClass;
374def IIC_SSE_CVT_PI2PS_RR : InstrItinClass;
375def IIC_SSE_CVT_PI2PS_RM : InstrItinClass;
376def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
377def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
378def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
379def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
380def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
381def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
382def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
383def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
384
385// MMX
386def IIC_MMX_MOV_MM_RM : InstrItinClass;
387def IIC_MMX_MOV_REG_MM : InstrItinClass;
388def IIC_MMX_MOVQ_RM : InstrItinClass;
389def IIC_MMX_MOVQ_RR : InstrItinClass;
390
391def IIC_MMX_ALU_RM : InstrItinClass;
392def IIC_MMX_ALU_RR : InstrItinClass;
393def IIC_MMX_ALUQ_RM : InstrItinClass;
394def IIC_MMX_ALUQ_RR : InstrItinClass;
395def IIC_MMX_PHADDSUBW_RM : InstrItinClass;
396def IIC_MMX_PHADDSUBW_RR : InstrItinClass;
397def IIC_MMX_PHADDSUBD_RM : InstrItinClass;
398def IIC_MMX_PHADDSUBD_RR : InstrItinClass;
399def IIC_MMX_PMUL : InstrItinClass;
400def IIC_MMX_MISC_FUNC_MEM : InstrItinClass;
401def IIC_MMX_MISC_FUNC_REG : InstrItinClass;
402def IIC_MMX_PSADBW : InstrItinClass;
403def IIC_MMX_SHIFT_RI : InstrItinClass;
404def IIC_MMX_SHIFT_RM : InstrItinClass;
405def IIC_MMX_SHIFT_RR : InstrItinClass;
406def IIC_MMX_UNPCK_H_RM : InstrItinClass;
407def IIC_MMX_UNPCK_H_RR : InstrItinClass;
408def IIC_MMX_UNPCK_L : InstrItinClass;
409def IIC_MMX_PCK_RM : InstrItinClass;
410def IIC_MMX_PCK_RR : InstrItinClass;
411def IIC_MMX_PSHUF : InstrItinClass;
412def IIC_MMX_PEXTR : InstrItinClass;
413def IIC_MMX_PINSRW : InstrItinClass;
414def IIC_MMX_MASKMOV : InstrItinClass;
415
416def IIC_MMX_CVT_PD_RR : InstrItinClass;
417def IIC_MMX_CVT_PD_RM : InstrItinClass;
418def IIC_MMX_CVT_PS_RR : InstrItinClass;
419def IIC_MMX_CVT_PS_RM : InstrItinClass;
420
421def IIC_CMPX_LOCK : InstrItinClass;
422def IIC_CMPX_LOCK_8 : InstrItinClass;
423def IIC_CMPX_LOCK_8B : InstrItinClass;
424def IIC_CMPX_LOCK_16B : InstrItinClass;
425
426def IIC_XADD_LOCK_MEM : InstrItinClass;
427def IIC_XADD_LOCK_MEM8 : InstrItinClass;
428
429def IIC_FILD : InstrItinClass;
430def IIC_FLD : InstrItinClass;
431def IIC_FLD80 : InstrItinClass;
432def IIC_FST : InstrItinClass;
433def IIC_FST80 : InstrItinClass;
434def IIC_FIST : InstrItinClass;
435def IIC_FLDZ : InstrItinClass;
436def IIC_FUCOM : InstrItinClass;
437def IIC_FUCOMI : InstrItinClass;
438def IIC_FCOMI : InstrItinClass;
439def IIC_FNSTSW : InstrItinClass;
440def IIC_FNSTCW : InstrItinClass;
441def IIC_FLDCW : InstrItinClass;
442def IIC_FNINIT : InstrItinClass;
443def IIC_FFREE : InstrItinClass;
444def IIC_FNCLEX : InstrItinClass;
445def IIC_WAIT : InstrItinClass;
446def IIC_FXAM : InstrItinClass;
447def IIC_FNOP : InstrItinClass;
448def IIC_FLDL : InstrItinClass;
449def IIC_F2XM1 : InstrItinClass;
450def IIC_FYL2X : InstrItinClass;
451def IIC_FPTAN : InstrItinClass;
452def IIC_FPATAN : InstrItinClass;
453def IIC_FXTRACT : InstrItinClass;
454def IIC_FPREM1 : InstrItinClass;
455def IIC_FPSTP : InstrItinClass;
456def IIC_FPREM : InstrItinClass;
457def IIC_FYL2XP1 : InstrItinClass;
458def IIC_FSINCOS : InstrItinClass;
459def IIC_FRNDINT : InstrItinClass;
460def IIC_FSCALE : InstrItinClass;
461def IIC_FCOMPP : InstrItinClass;
462def IIC_FXSAVE : InstrItinClass;
463def IIC_FXRSTOR : InstrItinClass;
464
465def IIC_FXCH : InstrItinClass;
466
467// System instructions
468def IIC_CPUID : InstrItinClass;
469def IIC_INT : InstrItinClass;
470def IIC_INT3 : InstrItinClass;
471def IIC_INVD : InstrItinClass;
472def IIC_INVLPG : InstrItinClass;
473def IIC_IRET : InstrItinClass;
474def IIC_HLT : InstrItinClass;
475def IIC_LXS : InstrItinClass;
476def IIC_LTR : InstrItinClass;
477def IIC_RDTSC : InstrItinClass;
478def IIC_RSM : InstrItinClass;
479def IIC_SIDT : InstrItinClass;
480def IIC_SGDT : InstrItinClass;
481def IIC_SLDT : InstrItinClass;
482def IIC_STR : InstrItinClass;
483def IIC_SWAPGS : InstrItinClass;
484def IIC_SYSCALL : InstrItinClass;
485def IIC_SYS_ENTER_EXIT : InstrItinClass;
486def IIC_IN_RR : InstrItinClass;
487def IIC_IN_RI : InstrItinClass;
488def IIC_OUT_RR : InstrItinClass;
489def IIC_OUT_IR : InstrItinClass;
490def IIC_INS : InstrItinClass;
491def IIC_MOV_REG_DR : InstrItinClass;
492def IIC_MOV_DR_REG : InstrItinClass;
493def IIC_MOV_REG_CR : InstrItinClass;
494def IIC_MOV_CR_REG : InstrItinClass;
495def IIC_MOV_REG_SR : InstrItinClass;
496def IIC_MOV_MEM_SR : InstrItinClass;
497def IIC_MOV_SR_REG : InstrItinClass;
498def IIC_MOV_SR_MEM : InstrItinClass;
499def IIC_LAR_RM : InstrItinClass;
500def IIC_LAR_RR : InstrItinClass;
501def IIC_LSL_RM : InstrItinClass;
502def IIC_LSL_RR : InstrItinClass;
503def IIC_LGDT : InstrItinClass;
504def IIC_LIDT : InstrItinClass;
505def IIC_LLDT_REG : InstrItinClass;
506def IIC_LLDT_MEM : InstrItinClass;
507def IIC_PUSH_CS : InstrItinClass;
508def IIC_PUSH_SR : InstrItinClass;
509def IIC_POP_SR : InstrItinClass;
510def IIC_POP_SR_SS : InstrItinClass;
511def IIC_VERR : InstrItinClass;
512def IIC_VERW_REG : InstrItinClass;
513def IIC_VERW_MEM : InstrItinClass;
514def IIC_WRMSR : InstrItinClass;
515def IIC_RDMSR : InstrItinClass;
516def IIC_RDPMC : InstrItinClass;
517def IIC_SMSW : InstrItinClass;
518def IIC_LMSW_REG : InstrItinClass;
519def IIC_LMSW_MEM : InstrItinClass;
520def IIC_ENTER : InstrItinClass;
521def IIC_LEAVE : InstrItinClass;
522def IIC_POP_MEM : InstrItinClass;
523def IIC_POP_REG16 : InstrItinClass;
524def IIC_POP_REG : InstrItinClass;
525def IIC_POP_F : InstrItinClass;
526def IIC_POP_FD : InstrItinClass;
527def IIC_POP_A : InstrItinClass;
528def IIC_PUSH_IMM : InstrItinClass;
529def IIC_PUSH_MEM : InstrItinClass;
530def IIC_PUSH_REG : InstrItinClass;
531def IIC_PUSH_F : InstrItinClass;
532def IIC_PUSH_A : InstrItinClass;
533def IIC_BSWAP : InstrItinClass;
534def IIC_BIT_SCAN_MEM : InstrItinClass;
535def IIC_BIT_SCAN_REG : InstrItinClass;
536def IIC_MOVS : InstrItinClass;
537def IIC_STOS : InstrItinClass;
538def IIC_SCAS : InstrItinClass;
539def IIC_CMPS : InstrItinClass;
540def IIC_MOV : InstrItinClass;
541def IIC_MOV_MEM : InstrItinClass;
542def IIC_AHF : InstrItinClass;
543def IIC_BT_MI : InstrItinClass;
544def IIC_BT_MR : InstrItinClass;
545def IIC_BT_RI : InstrItinClass;
546def IIC_BT_RR : InstrItinClass;
547def IIC_BTX_MI : InstrItinClass;
548def IIC_BTX_MR : InstrItinClass;
549def IIC_BTX_RI : InstrItinClass;
550def IIC_BTX_RR : InstrItinClass;
551def IIC_XCHG_REG : InstrItinClass;
552def IIC_XCHG_MEM : InstrItinClass;
553def IIC_XADD_REG : InstrItinClass;
554def IIC_XADD_MEM : InstrItinClass;
555def IIC_CMPXCHG_MEM : InstrItinClass;
556def IIC_CMPXCHG_REG : InstrItinClass;
557def IIC_CMPXCHG_MEM8 : InstrItinClass;
558def IIC_CMPXCHG_REG8 : InstrItinClass;
559def IIC_CMPXCHG_8B : InstrItinClass;
560def IIC_CMPXCHG_16B : InstrItinClass;
561def IIC_LODS : InstrItinClass;
562def IIC_OUTS : InstrItinClass;
563def IIC_CLC : InstrItinClass;
564def IIC_CLD : InstrItinClass;
565def IIC_CLI : InstrItinClass;
566def IIC_CMC : InstrItinClass;
567def IIC_CLTS : InstrItinClass;
568def IIC_STC : InstrItinClass;
569def IIC_STI : InstrItinClass;
570def IIC_STD : InstrItinClass;
571def IIC_XLAT : InstrItinClass;
572def IIC_AAA : InstrItinClass;
573def IIC_AAD : InstrItinClass;
574def IIC_AAM : InstrItinClass;
575def IIC_AAS : InstrItinClass;
576def IIC_DAA : InstrItinClass;
577def IIC_DAS : InstrItinClass;
578def IIC_BOUND : InstrItinClass;
579def IIC_ARPL_REG : InstrItinClass;
580def IIC_ARPL_MEM : InstrItinClass;
581def IIC_MOVBE : InstrItinClass;
582def IIC_AES   : InstrItinClass;
583def IIC_BLEND_MEM : InstrItinClass;
584def IIC_BLEND_NOMEM : InstrItinClass;
585def IIC_CBW   : InstrItinClass;
586def IIC_CRC32_REG : InstrItinClass;
587def IIC_CRC32_MEM : InstrItinClass;
588def IIC_SSE_DPPD_RR : InstrItinClass;
589def IIC_SSE_DPPD_RM : InstrItinClass;
590def IIC_SSE_DPPS_RR : InstrItinClass;
591def IIC_SSE_DPPS_RM : InstrItinClass;
592def IIC_MMX_EMMS : InstrItinClass;
593def IIC_SSE_EXTRACTPS_RR : InstrItinClass;
594def IIC_SSE_EXTRACTPS_RM : InstrItinClass;
595def IIC_SSE_INSERTPS_RR : InstrItinClass;
596def IIC_SSE_INSERTPS_RM : InstrItinClass;
597def IIC_SSE_MPSADBW_RR : InstrItinClass;
598def IIC_SSE_MPSADBW_RM : InstrItinClass;
599def IIC_SSE_PMULLD_RR : InstrItinClass;
600def IIC_SSE_PMULLD_RM : InstrItinClass;
601def IIC_SSE_ROUNDPS_REG : InstrItinClass;
602def IIC_SSE_ROUNDPS_MEM : InstrItinClass;
603def IIC_SSE_ROUNDPD_REG : InstrItinClass;
604def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
605def IIC_SSE_POPCNT_RR : InstrItinClass;
606def IIC_SSE_POPCNT_RM : InstrItinClass;
607def IIC_SSE_PCLMULQDQ_RR : InstrItinClass;
608def IIC_SSE_PCLMULQDQ_RM : InstrItinClass;
609
610def IIC_NOP : InstrItinClass;
611
612//===----------------------------------------------------------------------===//
613// Processor instruction itineraries.
614
615// IssueWidth is analogous to the number of decode units. Core and its
616// descendents, including Nehalem and SandyBridge have 4 decoders.
617// Resources beyond the decoder operate on micro-ops and are bufferred
618// so adjacent micro-ops don't directly compete.
619//
620// MicroOpBufferSize > 1 indicates that RAW dependencies can be
621// decoded in the same cycle. The value 32 is a reasonably arbitrary
622// number of in-flight instructions.
623//
624// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
625// indicates high latency opcodes. Alternatively, InstrItinData
626// entries may be included here to define specific operand
627// latencies. Since these latencies are not used for pipeline hazards,
628// they do not need to be exact.
629//
630// The GenericModel contains no instruction itineraries.
631def GenericModel : SchedMachineModel {
632  let IssueWidth = 4;
633  let MicroOpBufferSize = 32;
634  let LoadLatency = 4;
635  let HighLatency = 10;
636}
637
638include "X86ScheduleAtom.td"
639include "X86SchedSandyBridge.td"
640include "X86SchedHaswell.td"
641include "X86ScheduleSLM.td"
642