1; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s 2 3define i32 @icmp_eq_imm(i32 %a) nounwind ssp { 4entry: 5; CHECK: icmp_eq_imm 6; CHECK: cmp w0, #31 7; CHECK: cset w0, eq 8 %cmp = icmp eq i32 %a, 31 9 %conv = zext i1 %cmp to i32 10 ret i32 %conv 11} 12 13define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp { 14entry: 15; CHECK: icmp_eq_neg_imm 16; CHECK: cmn w0, #7 17; CHECK: cset w0, eq 18 %cmp = icmp eq i32 %a, -7 19 %conv = zext i1 %cmp to i32 20 ret i32 %conv 21} 22 23define i32 @icmp_eq(i32 %a, i32 %b) nounwind ssp { 24entry: 25; CHECK: icmp_eq 26; CHECK: cmp w0, w1 27; CHECK: cset w0, eq 28 %cmp = icmp eq i32 %a, %b 29 %conv = zext i1 %cmp to i32 30 ret i32 %conv 31} 32 33define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp { 34entry: 35; CHECK: icmp_ne 36; CHECK: cmp w0, w1 37; CHECK: cset w0, ne 38 %cmp = icmp ne i32 %a, %b 39 %conv = zext i1 %cmp to i32 40 ret i32 %conv 41} 42 43define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp { 44entry: 45; CHECK: icmp_ugt 46; CHECK: cmp w0, w1 47; CHECK: cset w0, hi 48 %cmp = icmp ugt i32 %a, %b 49 %conv = zext i1 %cmp to i32 50 ret i32 %conv 51} 52 53define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp { 54entry: 55; CHECK: icmp_uge 56; CHECK: cmp w0, w1 57; CHECK: cset w0, hs 58 %cmp = icmp uge i32 %a, %b 59 %conv = zext i1 %cmp to i32 60 ret i32 %conv 61} 62 63define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp { 64entry: 65; CHECK: icmp_ult 66; CHECK: cmp w0, w1 67; CHECK: cset w0, lo 68 %cmp = icmp ult i32 %a, %b 69 %conv = zext i1 %cmp to i32 70 ret i32 %conv 71} 72 73define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp { 74entry: 75; CHECK: icmp_ule 76; CHECK: cmp w0, w1 77; CHECK: cset w0, ls 78 %cmp = icmp ule i32 %a, %b 79 %conv = zext i1 %cmp to i32 80 ret i32 %conv 81} 82 83define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp { 84entry: 85; CHECK: icmp_sgt 86; CHECK: cmp w0, w1 87; CHECK: cset w0, gt 88 %cmp = icmp sgt i32 %a, %b 89 %conv = zext i1 %cmp to i32 90 ret i32 %conv 91} 92 93define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp { 94entry: 95; CHECK: icmp_sge 96; CHECK: cmp w0, w1 97; CHECK: cset w0, ge 98 %cmp = icmp sge i32 %a, %b 99 %conv = zext i1 %cmp to i32 100 ret i32 %conv 101} 102 103define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp { 104entry: 105; CHECK: icmp_slt 106; CHECK: cmp w0, w1 107; CHECK: cset w0, lt 108 %cmp = icmp slt i32 %a, %b 109 %conv = zext i1 %cmp to i32 110 ret i32 %conv 111} 112 113define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp { 114entry: 115; CHECK: icmp_sle 116; CHECK: cmp w0, w1 117; CHECK: cset w0, le 118 %cmp = icmp sle i32 %a, %b 119 %conv = zext i1 %cmp to i32 120 ret i32 %conv 121} 122 123define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp { 124entry: 125; CHECK: icmp_i64 126; CHECK: cmp x0, x1 127; CHECK: cset w{{[0-9]+}}, le 128 %cmp = icmp sle i64 %a, %b 129 %conv = zext i1 %cmp to i32 130 ret i32 %conv 131} 132 133define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp { 134entry: 135; CHECK: icmp_eq_i16 136; CHECK: sxth w0, w0 137; CHECK: sxth w1, w1 138; CHECK: cmp w0, w1 139; CHECK: cset w0, eq 140 %cmp = icmp eq i16 %a, %b 141 ret i1 %cmp 142} 143 144define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp { 145entry: 146; CHECK: icmp_eq_i8 147; CHECK: sxtb w0, w0 148; CHECK: sxtb w1, w1 149; CHECK: cmp w0, w1 150; CHECK: cset w0, eq 151 %cmp = icmp eq i8 %a, %b 152 ret i1 %cmp 153} 154 155define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { 156entry: 157; CHECK: icmp_i16_unsigned 158; CHECK: uxth w0, w0 159; CHECK: uxth w1, w1 160; CHECK: cmp w0, w1 161; CHECK: cset w0, lo 162 %cmp = icmp ult i16 %a, %b 163 %conv2 = zext i1 %cmp to i32 164 ret i32 %conv2 165} 166 167define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { 168entry: 169; CHECK: @icmp_i8_signed 170; CHECK: sxtb w0, w0 171; CHECK: sxtb w1, w1 172; CHECK: cmp w0, w1 173; CHECK: cset w0, gt 174 %cmp = icmp sgt i8 %a, %b 175 %conv2 = zext i1 %cmp to i32 176 ret i32 %conv2 177} 178 179 180define i32 @icmp_i16_signed_const(i16 %a) nounwind { 181entry: 182; CHECK: icmp_i16_signed_const 183; CHECK: sxth w0, w0 184; CHECK: cmn w0, #233 185; CHECK: cset w0, lt 186; CHECK: and w0, w0, #0x1 187 %cmp = icmp slt i16 %a, -233 188 %conv2 = zext i1 %cmp to i32 189 ret i32 %conv2 190} 191 192define i32 @icmp_i8_signed_const(i8 %a) nounwind { 193entry: 194; CHECK: icmp_i8_signed_const 195; CHECK: sxtb w0, w0 196; CHECK: cmp w0, #124 197; CHECK: cset w0, gt 198; CHECK: and w0, w0, #0x1 199 %cmp = icmp sgt i8 %a, 124 200 %conv2 = zext i1 %cmp to i32 201 ret i32 %conv2 202} 203 204define i32 @icmp_i1_unsigned_const(i1 %a) nounwind { 205entry: 206; CHECK: icmp_i1_unsigned_const 207; CHECK: and w0, w0, #0x1 208; CHECK: cmp w0, #0 209; CHECK: cset w0, lo 210; CHECK: and w0, w0, #0x1 211 %cmp = icmp ult i1 %a, 0 212 %conv2 = zext i1 %cmp to i32 213 ret i32 %conv2 214} 215