1; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s 2; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t 3; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA 4; REQUIRES: asserts 5 6; CHECK-SSA-LABEL: Machine code for function t1 7 8; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr 9; CHECK-SSA-NOT: [[QUOTREG]]<def> = 10; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]] 11 12; CHECK-SSA-LABEL: Machine code for function t2 13 14define i32 @t1(i32 %a, i32 %b) { 15; CHECK: @t1 16; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1 17; CHECK: msub w0, [[TMP]], w1, w0 18 %1 = srem i32 %a, %b 19 ret i32 %1 20} 21 22define i64 @t2(i64 %a, i64 %b) { 23; CHECK: @t2 24; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1 25; CHECK: msub x0, [[TMP]], x1, x0 26 %1 = srem i64 %a, %b 27 ret i64 %1 28} 29 30define i32 @t3(i32 %a, i32 %b) { 31; CHECK: @t3 32; CHECK: udiv [[TMP:w[0-9]+]], w0, w1 33; CHECK: msub w0, [[TMP]], w1, w0 34 %1 = urem i32 %a, %b 35 ret i32 %1 36} 37 38define i64 @t4(i64 %a, i64 %b) { 39; CHECK: @t4 40; CHECK: udiv [[TMP:x[0-9]+]], x0, x1 41; CHECK: msub x0, [[TMP]], x1, x0 42 %1 = urem i64 %a, %b 43 ret i64 %1 44} 45