1; Disable machine cse to stress the different path of the algorithm. 2; Otherwise, we always fall in the simple case, i.e., only one definition. 3; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone | FileCheck -check-prefix=PROMOTED %s 4; The REGULAR run just checks that the inputs passed to promote const expose 5; the appropriate patterns. 6; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-promote-const=false -mcpu=cyclone | FileCheck -check-prefix=REGULAR %s 7 8%struct.uint8x16x4_t = type { [4 x <16 x i8>] } 9 10; Constant is a structure 11define %struct.uint8x16x4_t @test1() { 12; PROMOTED-LABEL: test1: 13; Promote constant has created a big constant for the whole structure 14; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE 15; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF 16; Destination registers are defined by the ABI 17; PROMOTED-NEXT: ldp q0, q1, {{\[}}[[BASEADDR]]] 18; PROMOTED-NEXT: ldp q2, q3, {{\[}}[[BASEADDR]], #32] 19; PROMOTED-NEXT: ret 20 21; REGULAR-LABEL: test1: 22; Regular access is quite bad, it performs 4 loads, one for each chunk of 23; the structure 24; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 25; Destination registers are defined by the ABI 26; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 27; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 28; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 29; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE 30; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF] 31; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE 32; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF] 33; REGULAR-NEXT: ret 34entry: 35 ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] } 36} 37 38; Two different uses of the same constant in the same basic block 39define <16 x i8> @test2(<16 x i8> %arg) { 40entry: 41; PROMOTED-LABEL: test2: 42; In stress mode, constant vector are promoted 43; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE 44; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF 45; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] 46; Destination register is defined by ABI 47; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] 48; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]] 49; PROMOTED-NEXT: ret 50 51; REGULAR-LABEL: test2: 52; Regular access is strickly the same as promoted access. 53; The difference is that the address (and thus the space in memory) is not 54; shared between constants 55; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 56; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 57; Destination register is defined by ABI 58; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] 59; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]] 60; REGULAR-NEXT: ret 61 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 62 %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 63 %add.i9 = add <16 x i8> %add.i, %mul.i 64 ret <16 x i8> %add.i9 65} 66 67; Two different uses of the sane constant in two different basic blocks, 68; one dominates the other 69define <16 x i8> @test3(<16 x i8> %arg, i32 %path) { 70; PROMOTED-LABEL: test3: 71; In stress mode, constant vector are promoted 72; Since, the constant is the same as the previous function, 73; the same address must be used 74; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE 75; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF 76; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] 77; Destination register is defined by ABI 78; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] 79; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]] 80; Next BB 81; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE 82; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV2]]@PAGEOFF 83; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[BASEADDR]]] 84; Next BB 85; PROMOTED-NEXT: [[LABEL]]: 86; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 87; PROMOTED-NEXT: add.16b v0, v0, [[DESTV]] 88; PROMOTED-NEXT: ret 89 90; REGULAR-LABEL: test3: 91; Regular mode does not elimitate common sub expression by its own. 92; In other words, the same loads appears several times. 93; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1:lCP.*]]@PAGE 94; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF] 95; Destination register is defined by ABI 96; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] 97; REGULAR-NEXT: cbz w0, [[LABELelse:LBB.*]] 98; Next BB 99; Redundant load 100; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1]]@PAGE 101; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF] 102; REGULAR-NEXT: b [[LABELend:LBB.*]] 103; Next BB 104; REGULAR-NEXT: [[LABELelse]] 105; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE 106; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL2]]@PAGEOFF] 107; Next BB 108; REGULAR-NEXT: [[LABELend]]: 109; REGULAR-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 110; REGULAR-NEXT: add.16b v0, v0, [[DESTV]] 111; REGULAR-NEXT: ret 112entry: 113 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 114 %tobool = icmp eq i32 %path, 0 115 br i1 %tobool, label %if.else, label %if.then 116 117if.then: ; preds = %entry 118 %mul.i13 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 119 br label %if.end 120 121if.else: ; preds = %entry 122 %mul.i = mul <16 x i8> %add.i, <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85> 123 br label %if.end 124 125if.end: ; preds = %if.else, %if.then 126 %ret2.0 = phi <16 x i8> [ %mul.i13, %if.then ], [ %mul.i, %if.else ] 127 %add.i12 = add <16 x i8> %add.i, %ret2.0 128 ret <16 x i8> %add.i12 129} 130 131; Two different uses of the sane constant in two different basic blocks, 132; none dominates the other 133define <16 x i8> @test4(<16 x i8> %arg, i32 %path) { 134; PROMOTED-LABEL: test4: 135; In stress mode, constant vector are promoted 136; Since, the constant is the same as the previous function, 137; the same address must be used 138; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE 139; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF 140; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] 141; Destination register is defined by ABI 142; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] 143; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]] 144; Next BB 145; PROMOTED: mul.16b v0, v0, v[[REGNUM]] 146; Next BB 147; PROMOTED-NEXT: [[LABEL]]: 148; PROMOTED-NEXT: ret 149 150 151; REGULAR-LABEL: test4: 152; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE 153; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF] 154; Destination register is defined by ABI 155; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] 156; REGULAR-NEXT: cbz w0, [[LABEL:LBB.*]] 157; Next BB 158; Redundant expression 159; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3]]@PAGE 160; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF] 161; Destination register is defined by ABI 162; REGULAR-NEXT: mul.16b v0, v0, v[[REGNUM]] 163; Next BB 164; REGULAR-NEXT: [[LABEL]]: 165; REGULAR-NEXT: ret 166entry: 167 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 168 %tobool = icmp eq i32 %path, 0 169 br i1 %tobool, label %if.end, label %if.then 170 171if.then: ; preds = %entry 172 %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 173 br label %if.end 174 175if.end: ; preds = %entry, %if.then 176 %ret.0 = phi <16 x i8> [ %mul.i, %if.then ], [ %add.i, %entry ] 177 ret <16 x i8> %ret.0 178} 179 180; Two different uses of the sane constant in two different basic blocks, 181; one is in a phi. 182define <16 x i8> @test5(<16 x i8> %arg, i32 %path) { 183; PROMOTED-LABEL: test5: 184; In stress mode, constant vector are promoted 185; Since, the constant is the same as the previous function, 186; the same address must be used 187; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE 188; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF 189; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] 190; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]] 191; Next BB 192; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 193; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]] 194; Next BB 195; PROMOTED-NEXT: [[LABEL]]: 196; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]] 197; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]] 198; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]] 199; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]] 200; PROMOTED-NEXT: ret 201 202; REGULAR-LABEL: test5: 203; REGULAR: cbz w0, [[LABELelse:LBB.*]] 204; Next BB 205; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 206; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 207; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] 208; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]] 209; REGULAR-NEXT: b [[LABELend:LBB.*]] 210; Next BB 211; REGULAR-NEXT: [[LABELelse]] 212; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE 213; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] 214; Next BB 215; REGULAR-NEXT: [[LABELend]]: 216; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]] 217; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]] 218; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]] 219; REGULAR-NEXT: mul.16b v0, [[TMP3]], [[TMP3]] 220; REGULAR-NEXT: ret 221entry: 222 %tobool = icmp eq i32 %path, 0 223 br i1 %tobool, label %if.end, label %if.then 224 225if.then: ; preds = %entry 226 %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 227 %mul.i26 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> 228 br label %if.end 229 230if.end: ; preds = %entry, %if.then 231 %ret.0 = phi <16 x i8> [ %mul.i26, %if.then ], [ <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, %entry ] 232 %mul.i25 = mul <16 x i8> %ret.0, %ret.0 233 %mul.i24 = mul <16 x i8> %mul.i25, %mul.i25 234 %mul.i23 = mul <16 x i8> %mul.i24, %mul.i24 235 %mul.i = mul <16 x i8> %mul.i23, %mul.i23 236 ret <16 x i8> %mul.i 237} 238 239define void @accessBig(i64* %storage) { 240; PROMOTED-LABEL: accessBig: 241; PROMOTED: adrp 242; PROMOTED: ret 243 %addr = bitcast i64* %storage to <1 x i80>* 244 store <1 x i80> <i80 483673642326615442599424>, <1 x i80>* %addr 245 ret void 246} 247 248define void @asmStatement() { 249; PROMOTED-LABEL: asmStatement: 250; PROMOTED-NOT: adrp 251; PROMOTED: ret 252 call void asm sideeffect "bfxil w0, w0, $0, $1", "i,i"(i32 28, i32 4) 253 ret void 254} 255 256