1; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=ARM 2; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM 3; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO 4; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE 5; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4 6 7define void @test1(i32* %ptr, i32 %val1) { 8; ARM-LABEL: test1 9; ARM: dmb {{ish$}} 10; ARM-NEXT: str 11; ARM-NEXT: dmb {{ish$}} 12; THUMBONE-LABEL: test1 13; THUMBONE: __sync_lock_test_and_set_4 14; THUMBTWO-LABEL: test1 15; THUMBTWO: dmb {{ish$}} 16; THUMBTWO-NEXT: str 17; THUMBTWO-NEXT: dmb {{ish$}} 18 store atomic i32 %val1, i32* %ptr seq_cst, align 4 19 ret void 20} 21 22define i32 @test2(i32* %ptr) { 23; ARM-LABEL: test2 24; ARM: ldr 25; ARM-NEXT: dmb {{ish$}} 26; THUMBONE-LABEL: test2 27; THUMBONE: __sync_val_compare_and_swap_4 28; THUMBTWO-LABEL: test2 29; THUMBTWO: ldr 30; THUMBTWO-NEXT: dmb {{ish$}} 31 %val = load atomic i32* %ptr seq_cst, align 4 32 ret i32 %val 33} 34 35define void @test3(i8* %ptr1, i8* %ptr2) { 36; ARM-LABEL: test3 37; ARM-NOT: dmb 38; ARM: ldrb 39; ARM-NOT: dmb 40; ARM: strb 41; ARM-NOT: dmb 42; ARM: bx lr 43 44; THUMBTWO-LABEL: test3 45; THUMBTWO-NOT: dmb 46; THUMBTWO: ldrb 47; THUMBTWO-NOT: dmb 48; THUMBTWO: strb 49; THUMBTWO-NOT: dmb 50; THUMBTWO: bx lr 51 52; THUMBONE-LABEL: test3 53; THUMBONE-NOT: dmb 54; THUMBONE: ldrb 55; THUMBONE-NOT: dmb 56; THUMBONE: strb 57; THUMBONE-NOT: dmb 58 %val = load atomic i8* %ptr1 unordered, align 1 59 store atomic i8 %val, i8* %ptr2 unordered, align 1 60 ret void 61} 62 63define void @test4(i8* %ptr1, i8* %ptr2) { 64; THUMBONE-LABEL: test4 65; THUMBONE: ___sync_val_compare_and_swap_1 66; THUMBONE: ___sync_lock_test_and_set_1 67 %val = load atomic i8* %ptr1 seq_cst, align 1 68 store atomic i8 %val, i8* %ptr2 seq_cst, align 1 69 ret void 70} 71 72define i64 @test_old_load_64bit(i64* %p) { 73; ARMV4-LABEL: test_old_load_64bit 74; ARMV4: ___sync_val_compare_and_swap_8 75 %1 = load atomic i64* %p seq_cst, align 8 76 ret i64 %1 77} 78 79define void @test_old_store_64bit(i64* %p, i64 %v) { 80; ARMV4-LABEL: test_old_store_64bit 81; ARMV4: ___sync_lock_test_and_set_8 82 store atomic i64 %v, i64* %p seq_cst, align 8 83 ret void 84} 85