1; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s 2 3define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) { 4; CHECK-LABEL: vector_ext_2i8_to_2i64: 5; CHECK: vld1.16 {[[REG:d[0-9]+]] 6; CHECK: vmov.i64 {{q[0-9]+}}, #0xff 7; CHECK: vrev16.8 [[REG]], [[REG]] 8; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] 9 %1 = load <2 x i8>* %loadaddr 10 %2 = zext <2 x i8> %1 to <2 x i64> 11 store <2 x i64> %2, <2 x i64>* %storeaddr 12 ret void 13} 14 15define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) { 16; CHECK-LABEL: vector_ext_2i16_to_2i64: 17; CHECK: vld1.32 {[[REG:d[0-9]+]] 18; CHECK: vmov.i64 {{q[0-9]+}}, #0xffff 19; CHECK: vrev32.16 [[REG]], [[REG]] 20; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]] 21 %1 = load <2 x i16>* %loadaddr 22 %2 = zext <2 x i16> %1 to <2 x i64> 23 store <2 x i64> %2, <2 x i64>* %storeaddr 24 ret void 25} 26 27 28define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) { 29; CHECK-LABEL: vector_ext_2i8_to_2i32: 30; CHECK: vld1.16 {[[REG:d[0-9]+]] 31; CHECK: vrev16.8 [[REG]], [[REG]] 32 %1 = load <2 x i8>* %loadaddr 33 %2 = zext <2 x i8> %1 to <2 x i32> 34 store <2 x i32> %2, <2 x i32>* %storeaddr 35 ret void 36} 37 38define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) { 39; CHECK-LABEL: vector_ext_2i16_to_2i32: 40; CHECK: vld1.32 {[[REG:d[0-9]+]] 41; CHECK: vrev32.16 [[REG]], [[REG]] 42; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]] 43 %1 = load <2 x i16>* %loadaddr 44 %2 = zext <2 x i16> %1 to <2 x i32> 45 store <2 x i32> %2, <2 x i32>* %storeaddr 46 ret void 47} 48 49define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) { 50; CHECK-LABEL: vector_ext_2i8_to_2i16: 51; CHECK: vld1.16 {[[REG:d[0-9]+]] 52; CHECK: vrev16.8 [[REG]], [[REG]] 53; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] 54 %1 = load <2 x i8>* %loadaddr 55 %2 = zext <2 x i8> %1 to <2 x i16> 56 store <2 x i16> %2, <2 x i16>* %storeaddr 57 ret void 58} 59 60define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) { 61; CHECK-LABEL: vector_ext_4i8_to_4i32: 62; CHECK: vld1.32 {[[REG:d[0-9]+]] 63; CHECK: vrev32.8 [[REG]], [[REG]] 64; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] 65 %1 = load <4 x i8>* %loadaddr 66 %2 = zext <4 x i8> %1 to <4 x i32> 67 store <4 x i32> %2, <4 x i32>* %storeaddr 68 ret void 69} 70 71define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) { 72; CHECK-LABEL: vector_ext_4i8_to_4i16: 73; CHECK: vld1.32 {[[REG:d[0-9]+]] 74; CHECK: vrev32.8 [[REG]], [[REG]] 75; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] 76 %1 = load <4 x i8>* %loadaddr 77 %2 = zext <4 x i8> %1 to <4 x i16> 78 store <4 x i16> %2, <4 x i16>* %storeaddr 79 ret void 80} 81 82