1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s 2; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s 3 4@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4 5@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4 6 7; EG-CHECK: @local_memory_two_objects 8 9; Check that the LDS size emitted correctly 10; EG-CHECK: .long 166120 11; EG-CHECK-NEXT: .long 8 12; SI-CHECK: .long 47180 13; SI-CHECK-NEXT: .long 32768 14 15; We would like to check the the lds writes are using different 16; addresses, but due to variations in the scheduler, we can't do 17; this consistently on evergreen GPUs. 18; EG-CHECK: LDS_WRITE 19; EG-CHECK: LDS_WRITE 20; SI-CHECK: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]] 21; SI-CHECK-NOT: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW]] 22 23; GROUP_BARRIER must be the last instruction in a clause 24; EG-CHECK: GROUP_BARRIER 25; EG-CHECK-NEXT: ALU clause 26 27; Make sure the lds reads are using different addresses, at different 28; constant offsets. 29; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] 30; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] 31; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 0x10 32; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0x0, 33 34define void @local_memory_two_objects(i32 addrspace(1)* %out) { 35entry: 36 %x.i = call i32 @llvm.r600.read.tidig.x() #0 37 %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i 38 store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4 39 %mul = shl nsw i32 %x.i, 1 40 %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i 41 store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4 42 %sub = sub nsw i32 3, %x.i 43 call void @llvm.AMDGPU.barrier.local() 44 %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub 45 %0 = load i32 addrspace(3)* %arrayidx2, align 4 46 %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i 47 store i32 %0, i32 addrspace(1)* %arrayidx3, align 4 48 %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub 49 %1 = load i32 addrspace(3)* %arrayidx4, align 4 50 %add = add nsw i32 %x.i, 4 51 %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add 52 store i32 %1, i32 addrspace(1)* %arrayidx5, align 4 53 ret void 54} 55 56declare i32 @llvm.r600.read.tidig.x() #0 57declare void @llvm.AMDGPU.barrier.local() 58 59attributes #0 = { readnone } 60