1; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s 2; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s 3 4; Test all the cmp predicates that can feed an integer conditional move. 5 6define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) { 7; CHECK-LABEL: select_fcmp_false_cmov 8; CHECK: movq %rsi, %rax 9; CHECK-NEXT: retq 10 %1 = fcmp false double %a, %b 11 %2 = select i1 %1, i64 %c, i64 %d 12 ret i64 %2 13} 14 15define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) { 16; CHECK-LABEL: select_fcmp_oeq_cmov 17; CHECK: ucomisd %xmm1, %xmm0 18; CHECK-NEXT: setnp %al 19; CHECK-NEXT: sete %cl 20; CHECK-NEXT: testb %al, %cl 21; CHECK-NEXT: cmoveq %rsi, %rdi 22 %1 = fcmp oeq double %a, %b 23 %2 = select i1 %1, i64 %c, i64 %d 24 ret i64 %2 25} 26 27define i64 @select_fcmp_ogt_cmov(double %a, double %b, i64 %c, i64 %d) { 28; CHECK-LABEL: select_fcmp_ogt_cmov 29; CHECK: ucomisd %xmm1, %xmm0 30; CHECK-NEXT: cmovbeq %rsi, %rdi 31 %1 = fcmp ogt double %a, %b 32 %2 = select i1 %1, i64 %c, i64 %d 33 ret i64 %2 34} 35 36define i64 @select_fcmp_oge_cmov(double %a, double %b, i64 %c, i64 %d) { 37; CHECK-LABEL: select_fcmp_oge_cmov 38; CHECK: ucomisd %xmm1, %xmm0 39; CHECK-NEXT: cmovbq %rsi, %rdi 40 %1 = fcmp oge double %a, %b 41 %2 = select i1 %1, i64 %c, i64 %d 42 ret i64 %2 43} 44 45define i64 @select_fcmp_olt_cmov(double %a, double %b, i64 %c, i64 %d) { 46; CHECK-LABEL: select_fcmp_olt_cmov 47; CHECK: ucomisd %xmm0, %xmm1 48; CHECK-NEXT: cmovbeq %rsi, %rdi 49 %1 = fcmp olt double %a, %b 50 %2 = select i1 %1, i64 %c, i64 %d 51 ret i64 %2 52} 53 54define i64 @select_fcmp_ole_cmov(double %a, double %b, i64 %c, i64 %d) { 55; CHECK-LABEL: select_fcmp_ole_cmov 56; CHECK: ucomisd %xmm0, %xmm1 57; CHECK-NEXT: cmovbq %rsi, %rdi 58 %1 = fcmp ole double %a, %b 59 %2 = select i1 %1, i64 %c, i64 %d 60 ret i64 %2 61} 62 63define i64 @select_fcmp_one_cmov(double %a, double %b, i64 %c, i64 %d) { 64; CHECK-LABEL: select_fcmp_one_cmov 65; CHECK: ucomisd %xmm1, %xmm0 66; CHECK-NEXT: cmoveq %rsi, %rdi 67 %1 = fcmp one double %a, %b 68 %2 = select i1 %1, i64 %c, i64 %d 69 ret i64 %2 70} 71 72define i64 @select_fcmp_ord_cmov(double %a, double %b, i64 %c, i64 %d) { 73; CHECK-LABEL: select_fcmp_ord_cmov 74; CHECK: ucomisd %xmm1, %xmm0 75; CHECK-NEXT: cmovpq %rsi, %rdi 76 %1 = fcmp ord double %a, %b 77 %2 = select i1 %1, i64 %c, i64 %d 78 ret i64 %2 79} 80 81define i64 @select_fcmp_uno_cmov(double %a, double %b, i64 %c, i64 %d) { 82; CHECK-LABEL: select_fcmp_uno_cmov 83; CHECK: ucomisd %xmm1, %xmm0 84; CHECK-NEXT: cmovnpq %rsi, %rdi 85 %1 = fcmp uno double %a, %b 86 %2 = select i1 %1, i64 %c, i64 %d 87 ret i64 %2 88} 89 90define i64 @select_fcmp_ueq_cmov(double %a, double %b, i64 %c, i64 %d) { 91; CHECK-LABEL: select_fcmp_ueq_cmov 92; CHECK: ucomisd %xmm1, %xmm0 93; CHECK-NEXT: cmovneq %rsi, %rdi 94 %1 = fcmp ueq double %a, %b 95 %2 = select i1 %1, i64 %c, i64 %d 96 ret i64 %2 97} 98 99define i64 @select_fcmp_ugt_cmov(double %a, double %b, i64 %c, i64 %d) { 100; CHECK-LABEL: select_fcmp_ugt_cmov 101; CHECK: ucomisd %xmm0, %xmm1 102; CHECK-NEXT: cmovaeq %rsi, %rdi 103 %1 = fcmp ugt double %a, %b 104 %2 = select i1 %1, i64 %c, i64 %d 105 ret i64 %2 106} 107 108define i64 @select_fcmp_uge_cmov(double %a, double %b, i64 %c, i64 %d) { 109; CHECK-LABEL: select_fcmp_uge_cmov 110; CHECK: ucomisd %xmm0, %xmm1 111; CHECK-NEXT: cmovaq %rsi, %rdi 112 %1 = fcmp uge double %a, %b 113 %2 = select i1 %1, i64 %c, i64 %d 114 ret i64 %2 115} 116 117define i64 @select_fcmp_ult_cmov(double %a, double %b, i64 %c, i64 %d) { 118; CHECK-LABEL: select_fcmp_ult_cmov 119; CHECK: ucomisd %xmm1, %xmm0 120; CHECK-NEXT: cmovaeq %rsi, %rdi 121 %1 = fcmp ult double %a, %b 122 %2 = select i1 %1, i64 %c, i64 %d 123 ret i64 %2 124} 125 126define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) { 127; CHECK-LABEL: select_fcmp_ule_cmov 128; CHECK: ucomisd %xmm1, %xmm0 129; CHECK-NEXT: cmovaq %rsi, %rdi 130 %1 = fcmp ule double %a, %b 131 %2 = select i1 %1, i64 %c, i64 %d 132 ret i64 %2 133} 134 135define i64 @select_fcmp_une_cmov(double %a, double %b, i64 %c, i64 %d) { 136; CHECK-LABEL: select_fcmp_une_cmov 137; CHECK: ucomisd %xmm1, %xmm0 138; CHECK-NEXT: setp %al 139; CHECK-NEXT: setne %cl 140; CHECK-NEXT: orb %al, %cl 141; CHECK-NEXT: cmoveq %rsi, %rdi 142 %1 = fcmp une double %a, %b 143 %2 = select i1 %1, i64 %c, i64 %d 144 ret i64 %2 145} 146 147define i64 @select_fcmp_true_cmov(double %a, double %b, i64 %c, i64 %d) { 148; CHECK-LABEL: select_fcmp_true_cmov 149; CHECK: movq %rdi, %rax 150 %1 = fcmp true double %a, %b 151 %2 = select i1 %1, i64 %c, i64 %d 152 ret i64 %2 153} 154 155define i64 @select_icmp_eq_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 156; CHECK-LABEL: select_icmp_eq_cmov 157; CHECK: cmpq %rsi, %rdi 158; CHECK-NEXT: cmovneq %rcx, %rdx 159; CHECK-NEXT: movq %rdx, %rax 160 %1 = icmp eq i64 %a, %b 161 %2 = select i1 %1, i64 %c, i64 %d 162 ret i64 %2 163} 164 165define i64 @select_icmp_ne_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 166; CHECK-LABEL: select_icmp_ne_cmov 167; CHECK: cmpq %rsi, %rdi 168; CHECK-NEXT: cmoveq %rcx, %rdx 169; CHECK-NEXT: movq %rdx, %rax 170 %1 = icmp ne i64 %a, %b 171 %2 = select i1 %1, i64 %c, i64 %d 172 ret i64 %2 173} 174 175define i64 @select_icmp_ugt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 176; CHECK-LABEL: select_icmp_ugt_cmov 177; CHECK: cmpq %rsi, %rdi 178; CHECK-NEXT: cmovbeq %rcx, %rdx 179; CHECK-NEXT: movq %rdx, %rax 180 %1 = icmp ugt i64 %a, %b 181 %2 = select i1 %1, i64 %c, i64 %d 182 ret i64 %2 183} 184 185 186define i64 @select_icmp_uge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 187; CHECK-LABEL: select_icmp_uge_cmov 188; CHECK: cmpq %rsi, %rdi 189; CHECK-NEXT: cmovbq %rcx, %rdx 190; CHECK-NEXT: movq %rdx, %rax 191 %1 = icmp uge i64 %a, %b 192 %2 = select i1 %1, i64 %c, i64 %d 193 ret i64 %2 194} 195 196define i64 @select_icmp_ult_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 197; CHECK-LABEL: select_icmp_ult_cmov 198; CHECK: cmpq %rsi, %rdi 199; CHECK-NEXT: cmovaeq %rcx, %rdx 200; CHECK-NEXT: movq %rdx, %rax 201 %1 = icmp ult i64 %a, %b 202 %2 = select i1 %1, i64 %c, i64 %d 203 ret i64 %2 204} 205 206define i64 @select_icmp_ule_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 207; CHECK-LABEL: select_icmp_ule_cmov 208; CHECK: cmpq %rsi, %rdi 209; CHECK-NEXT: cmovaq %rcx, %rdx 210; CHECK-NEXT: movq %rdx, %rax 211 %1 = icmp ule i64 %a, %b 212 %2 = select i1 %1, i64 %c, i64 %d 213 ret i64 %2 214} 215 216define i64 @select_icmp_sgt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 217; CHECK-LABEL: select_icmp_sgt_cmov 218; CHECK: cmpq %rsi, %rdi 219; CHECK-NEXT: cmovleq %rcx, %rdx 220; CHECK-NEXT: movq %rdx, %rax 221 %1 = icmp sgt i64 %a, %b 222 %2 = select i1 %1, i64 %c, i64 %d 223 ret i64 %2 224} 225 226define i64 @select_icmp_sge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 227; CHECK-LABEL: select_icmp_sge_cmov 228; CHECK: cmpq %rsi, %rdi 229; CHECK-NEXT: cmovlq %rcx, %rdx 230; CHECK-NEXT: movq %rdx, %rax 231 %1 = icmp sge i64 %a, %b 232 %2 = select i1 %1, i64 %c, i64 %d 233 ret i64 %2 234} 235 236define i64 @select_icmp_slt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 237; CHECK-LABEL: select_icmp_slt_cmov 238; CHECK: cmpq %rsi, %rdi 239; CHECK-NEXT: cmovgeq %rcx, %rdx 240; CHECK-NEXT: movq %rdx, %rax 241 %1 = icmp slt i64 %a, %b 242 %2 = select i1 %1, i64 %c, i64 %d 243 ret i64 %2 244} 245 246define i64 @select_icmp_sle_cmov(i64 %a, i64 %b, i64 %c, i64 %d) { 247; CHECK-LABEL: select_icmp_sle_cmov 248; CHECK: cmpq %rsi, %rdi 249; CHECK-NEXT: cmovgq %rcx, %rdx 250; CHECK-NEXT: movq %rdx, %rax 251 %1 = icmp sle i64 %a, %b 252 %2 = select i1 %1, i64 %c, i64 %d 253 ret i64 %2 254} 255 256