1; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s 2 3; widening shuffle v3float and then a add 4define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { 5entry: 6; CHECK-LABEL: shuf: 7; CHECK: extractps 8; CHECK: extractps 9 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2> 10 %val = fadd <3 x float> %x, %src2 11 store <3 x float> %val, <3 x float>* %dst.addr 12 ret void 13; CHECK: ret 14} 15 16 17; widening shuffle v3float with a different mask and then a add 18define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { 19entry: 20; CHECK-LABEL: shuf2: 21; CHECK: extractps 22; CHECK: extractps 23 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2> 24 %val = fadd <3 x float> %x, %src2 25 store <3 x float> %val, <3 x float>* %dst.addr 26 ret void 27; CHECK: ret 28} 29 30; Example of when widening a v3float operation causes the DAG to replace a node 31; with the operation that we are currently widening, i.e. when replacing 32; opA with opB, the DAG will produce new operations with opA. 33define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind { 34entry: 35; CHECK-LABEL: shuf3: 36; CHECK-NOT: movlhps 37; CHECK-NOT: shufps 38; CHECK: pshufd 39 %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5> 40 %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 41 %tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 42 %tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>> 43 %tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 44 %tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 45 %tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2> 46 %t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32> 47 %shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19> 48 %and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080> 49 %shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3> 50 store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst 51 ret void 52; CHECK: ret 53} 54 55; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS 56define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone { 57; CHECK-LABEL: shuf4: 58; CHECK-NOT: punpckldq 59 %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 60 ret <8 x i8> %vshuf 61; CHECK: ret 62} 63 64; PR11389: another CONCAT_VECTORS case 65define void @shuf5(<8 x i8>* %p) nounwind { 66; CHECK-LABEL: shuf5: 67 %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 68 store <8 x i8> %v, <8 x i8>* %p, align 8 69 ret void 70; CHECK: ret 71} 72