| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 230 const MCInstrDesc &MCID) { in BuildMI()
239 const MCInstrDesc &MCID, in BuildMI()
252 const MCInstrDesc &MCID, in BuildMI()
263 const MCInstrDesc &MCID, in BuildMI()
274 const MCInstrDesc &MCID, in BuildMI()
292 const MCInstrDesc &MCID) { in BuildMI()
302 const MCInstrDesc &MCID) { in BuildMI()
312 const MCInstrDesc &MCID) { in BuildMI()
328 const MCInstrDesc &MCID) { in BuildMI()
338 const MCInstrDesc &MCID, in BuildMI()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore() local
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet() local
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother() local
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType() local
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| D | PPCRegisterInfo.cpp | 955 const MCInstrDesc &MCID = TII.get(ADDriOpc); in materializeFrameBaseRegister() local
980 const MCInstrDesc &MCID = MI.getDesc(); in resolveFrameIndex() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
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| D | ARMCodeEmitter.cpp | 453 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue() local
766 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction() local
920 const MCInstrDesc &MCID, in getMachineSoRegOpValue()
1002 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction() local
1100 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction() local
1178 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscLoadStoreInstruction() local
1263 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreMultipleInstruction() local
1303 const MCInstrDesc &MCID = MI.getDesc(); in emitMulFrmInstruction() local
1340 const MCInstrDesc &MCID = MI.getDesc(); in emitExtendInstruction() local
1377 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscArithInstruction() local
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| D | Thumb2SizeReduction.cpp | 213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
549 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
698 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
762 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow() local
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| D | MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
344 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
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| D | Thumb1RegisterInfo.cpp | 239 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate() local
289 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate() local
317 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant() local
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| D | Thumb2ITBlockPass.cpp | 142 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
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| /external/llvm/lib/CodeGen/ |
| D | ScoreboardHazardRecognizer.cpp | 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
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| D | TargetInstrInfo.cpp | 42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
123 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
186 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
221 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
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| D | PeepholeOptimizer.cpp | 606 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable() local
626 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local
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| D | SystemZInstrInfo.cpp | 195 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleMove() local
624 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleBD12Move() local
1123 const MCInstrDesc &MCID = get(Opcode); in getOpcodeForOffset() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInst.h | 27 const MCInstrDesc *MCID; variable
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| /external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| D | SkPdfMarkedContentReferenceDictionary_autogen.cpp | 59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { in MCID() function in SkPdfMarkedContentReferenceDictionary
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| /external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| D | SkPdfMarkedContentReferenceDictionary_autogen.cpp | 59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { in MCID() function in SkPdfMarkedContentReferenceDictionary
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionalCompares.cpp | 593 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
650 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
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| D | AArch64RegisterInfo.cpp | 294 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); in materializeFrameBaseRegister() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
436 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
514 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
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| D | ScheduleDAGSDNodes.cpp | 305 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
440 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
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| D | InstrEmitter.cpp | 320 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() local
843 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
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| D | ScheduleDAGRRList.cpp | 1004 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
1194 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1320 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
2685 const MCInstrDesc &MCID = TII->get(Opc); in canClobber() local
2912 const MCInstrDesc &MCID = TII->get(Opc); in AddPseudoTwoAddrDeps() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 153 const MCInstrDesc &MCID = MI->getDesc(); variable
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 102 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
|