Home
last modified time | relevance | path

Searched defs:Opc (Results 1 – 25 of 121) sorted by relevance

12345

/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h348 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
353 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
358 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
364 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
368 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
374 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
DARMISelDAGToDAG.cpp118 SDValue &Opc) { in SelectAddrMode2Base()
123 SDValue &Opc) { in SelectAddrMode2ShOp()
128 SDValue &Opc) { in SelectAddrMode2()
298 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
469 SDValue &Opc, in SelectImmShifterOperand()
493 SDValue &Opc, in SelectRegShifterOperand()
570 SDValue &Opc) { in SelectLdStSOReg()
669 SDValue &Opc) { in SelectAddrMode2Worker()
804 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
840 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
[all …]
DARMFastISel.cpp476 unsigned Opc; in ARMMaterializeFP() local
501 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
520 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
536 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
595 unsigned Opc; in ARMMaterializeGV() local
633 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; in ARMMaterializeGV() local
649 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
714 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in TargetMaterializeAlloca() local
892 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
960 unsigned Opc; in ARMEmitLoad() local
[all …]
DARMLoadStoreOptimizer.cpp290 static bool isT1i32Load(unsigned Opc) { in isT1i32Load()
294 static bool isT2i32Load(unsigned Opc) { in isT2i32Load()
298 static bool isi32Load(unsigned Opc) { in isi32Load()
302 static bool isT1i32Store(unsigned Opc) { in isT1i32Store()
306 static bool isT2i32Store(unsigned Opc) { in isT2i32Store()
310 static bool isi32Store(unsigned Opc) { in isi32Store()
314 static unsigned getImmScale(unsigned Opc) { in getImmScale()
343 unsigned Opc = MBBI->getOpcode(); in UpdateBaseRegUses() local
904 static unsigned getUpdatingLSMultipleOpcode(unsigned Opc, in getUpdatingLSMultipleOpcode()
1069 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc, in getPreIndexedLoadStoreOpcode()
[all …]
DARMInstrInfo.cpp125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? in runOnMachineFunction() local
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h208 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
210 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
227 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } in isIndirectBranchOpcode()
DAArch64LoadStoreOptimizer.cpp113 static bool isUnscaledLdst(unsigned Opc) { in isUnscaledLdst()
178 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode()
215 static unsigned getPreIndexedOpcode(unsigned Opc) { in getPreIndexedOpcode()
242 static unsigned getPostIndexedOpcode(unsigned Opc) { in getPostIndexedOpcode()
392 int Opc = FirstMI->getOpcode(); in findMatchingInsn() local
837 int Opc = MI->getOpcode(); in optimizeBlock() local
DAArch64ISelDAGToDAG.cpp209 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc, in isOpcWithIntImmediate()
879 unsigned Opc, bool isExt) { in SelectTable()
991 unsigned Opc, unsigned SubRegIdx) { in SelectLoad()
1015 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad()
1050 unsigned Opc) { in SelectStore()
1069 unsigned Opc) { in SelectPostStore()
1125 unsigned Opc) { in SelectLoadLane()
1170 unsigned Opc) { in SelectPostLoadLane()
1228 unsigned Opc) { in SelectStoreLane()
1261 unsigned Opc) { in SelectPostStoreLane()
[all …]
DAArch64BranchRelaxation.cpp274 static bool isConditionalBranch(unsigned Opc) { in isConditionalBranch()
309 static unsigned getOppositeConditionOpcode(unsigned Opc) { in getOppositeConditionOpcode()
325 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits()
DAArch64AdvSIMDScalarPass.cpp160 static int getTransformOpcode(unsigned Opc) { in getTransformOpcode()
175 int Opc = MI->getOpcode(); in isTransformable() local
DAArch64InstrInfo.cpp313 unsigned Opc = 0; in canFoldIntoCSel() local
494 unsigned Opc = 0; in insertSelect() local
839 unsigned Opc = Instr.getOpcode(); in optimizeCompareInstr() local
1596 unsigned Opc = 0; in storeRegToStackSlot() local
1694 unsigned Opc = 0; in loadRegFromStackSlot() local
1800 unsigned Opc; in emitFrameOffset() local
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp97 MachineInstrBuilder EmitInst(unsigned Opc) { in EmitInst()
101 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) { in EmitInst()
106 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg, in EmitInstStore()
111 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg, in EmitInstLoad()
160 unsigned Opc; in EmitLoad() local
219 unsigned Opc; in EmitStore() local
375 unsigned Opc = Mips::ADDiu; in Materialize32BitInt() local
DMipsSEInstrInfo.cpp45 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
68 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
86 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
191 unsigned Opc = 0; in storeRegToStack() local
232 unsigned Opc = 0; in loadRegFromStack() local
269 unsigned Opc; in expandPostRAPseudo() local
442 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
DMips16InstrInfo.cpp68 unsigned Opc = 0; in copyPhysReg() local
104 unsigned Opc = 0; in storeRegToStack() local
120 unsigned Opc = 0; in loadRegFromStack() local
206 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; in makeFrame() local
236 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? in restoreFrame() local
DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member
DMips16ISelDAGToDAG.cpp46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, in selectMULT()
259 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectNode() local
DMipsInstrInfo.cpp71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, in AnalyzeCondBr()
101 unsigned Opc = Cond[0].getImm(); in BuildCondBr() local
/external/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
67 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
114 int Opc = MI->getOpcode(); in runOnMachineFunction() local
DHexagonExpandPredSpillCode.cpp85 int Opc = MI->getOpcode(); in runOnMachineFunction() local
DHexagonSplitConst32AndConst64.cpp87 int Opc = MI->getOpcode(); in runOnMachineFunction() local
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp108 unsigned Opc = MBBI->getOpcode(); in findDeadCallerSavedReg() local
155 unsigned Opc; in emitSPUpdate() local
212 unsigned Opc = PI->getOpcode(); in mergeSPUpdatesUp() local
243 unsigned Opc = NI->getOpcode(); in mergeSPUpdatesDown() local
275 unsigned Opc = PI->getOpcode(); in mergeSPUpdates() local
807 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr; in emitPrologue() local
909 unsigned Opc = PI->getOpcode(); in emitEpilogue() local
933 unsigned Opc = getLEArOpcode(IsLP64); in emitEpilogue() local
937 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); in emitEpilogue() local
1164 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; in spillCalleeSavedRegisters() local
[all …]
DX86InstrInfo.cpp1814 unsigned Opc = Orig->getOpcode(); in reMaterialize() local
1863 unsigned Opc, bool AllowSP, in classifyLEAReg()
1950 unsigned Opc, leaInReg; in convertToThreeAddressWithLEA() local
2130 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2171 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
2202 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
2236 unsigned Opc; in convertToThreeAddress() local
2310 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2369 unsigned Opc; in commuteInstruction() local
2406 unsigned Opc; in commuteInstruction() local
[all …]
DX86FastISel.cpp367 unsigned Opc = 0; in X86FastEmitLoad() local
429 unsigned Opc = 0; in X86FastEmitStore() local
495 unsigned Opc = 0; in X86FastEmitStore() local
532 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
593 unsigned Opc = 0; in handleConstantAddresses() local
1264 unsigned Opc = X86::getSETFromCond(CC); in X86SelectCmp() local
1842 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize()); in X86FastEmitCMoveSelect() local
1897 unsigned *Opc = nullptr; in X86FastEmitSSESelect() local
1938 unsigned Opc; in X86FastEmitPseudoSelect() local
2192 unsigned Opc; in X86VisitIntrinsicCall() local
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp430 unsigned Opc; in PPCEmitLoad() local
570 unsigned Opc; in PPCEmitStore() local
971 unsigned Opc; in SelectIToFP() local
1064 unsigned Opc; in SelectFPToI() local
1106 unsigned Opc; in SelectBinaryIntOp() local
1633 unsigned Opc; in PPCEmitIntExt() local
1830 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; in PPCMaterializeFP() local
2031 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; in PPCMaterializeInt() local
2180 unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) { in FastEmit_i()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp344 unsigned Opc; in SelectAddrSpaceCast() local
369 unsigned Opc; in SelectAddrSpaceCast() local
2399 unsigned Opc = 0; in SelectLoadParam() local
2787 unsigned Opc = 0; in SelectTextureIntrinsic() local
2931 unsigned Opc = 0; in SelectSurfaceIntrinsic() local
3442 unsigned Opc; in SelectBFE() local

12345