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Searched defs:Reg (Results 1 – 25 of 260) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands()
244 reg_instructions(unsigned Reg) const { in reg_instructions()
260 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles()
281 reg_nodbg_operands(unsigned Reg) const { in reg_nodbg_operands()
299 reg_nodbg_instructions(unsigned Reg) const { in reg_nodbg_instructions()
317 reg_nodbg_bundles(unsigned Reg) const { in reg_nodbg_bundles()
336 inline iterator_range<def_iterator> def_operands(unsigned Reg) const { in def_operands()
352 def_instructions(unsigned Reg) const { in def_instructions()
368 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const { in def_bundles()
394 inline iterator_range<use_iterator> use_operands(unsigned Reg) const { in use_operands()
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DLivePhysRegs.h74 void addReg(unsigned Reg) { in addReg()
84 void removeReg(unsigned Reg) { in removeReg()
101 bool contains(unsigned Reg) const { return LiveRegs.count(Reg); } in contains()
DLiveIntervalAnalysis.h108 LiveInterval &getInterval(unsigned Reg) { in getInterval()
115 const LiveInterval &getInterval(unsigned Reg) const { in getInterval()
119 bool hasInterval(unsigned Reg) const { in hasInterval()
124 LiveInterval &createEmptyInterval(unsigned Reg) { in createEmptyInterval()
131 LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) { in createAndComputeVirtRegInterval()
138 void removeInterval(unsigned Reg) { in removeInterval()
DLiveVariables.h281 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { in isLiveIn()
299 bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); } in isPHIJoin()
302 void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); } in setPHIJoin()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup()
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup()
107 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive()
161 unsigned Reg = *AI; in StartBlock() local
174 unsigned Reg = *I; in StartBlock() local
204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
230 unsigned Reg = MO.getReg(); in IsImplicitDefUse() local
250 const unsigned Reg = MO.getReg(); in GetPassthruRegs() local
265 unsigned Reg = P->getReg(); in AntiDepEdges() local
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DLivePhysRegs.cpp42 unsigned Reg = O->getReg(); in stepBackward() local
54 unsigned Reg = O->getReg(); in stepBackward() local
70 unsigned Reg = O->getReg(); in stepForward() local
DDeadMachineInstructionElim.cpp70 unsigned Reg = MO.getReg(); in isDead() local
131 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
149 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
168 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse()
281 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) { in FindLastRefOrPartRef()
311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { in HandlePhysRegKill()
426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
443 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, in HandlePhysRegDef()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs() local
651 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
676 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, in replaceKillInstruction()
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DMachineInstrBundle.cpp133 unsigned Reg = MO.getReg(); in finalizeBundle() local
156 unsigned Reg = MO.getReg(); in finalizeBundle() local
187 unsigned Reg = LocalDefs[i]; in finalizeBundle() local
197 unsigned Reg = ExternUses[i]; in finalizeBundle() local
252 MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg, in analyzeVirtReg()
281 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg, in analyzePhysReg()
DCriticalAntiDepBreaker.cpp67 unsigned Reg = *AI; in StartBlock() local
82 unsigned Reg = *AI; in StartBlock() local
108 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
180 unsigned Reg = MO.getReg(); in PrescanInstruction() local
266 unsigned Reg = MO.getReg(); in ScanInstruction() local
303 unsigned Reg = MO.getReg(); in ScanInstruction() local
475 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { in BreakAntiDependencies() local
624 unsigned Reg = MO.getReg(); in BreakAntiDependencies() local
DRegisterPressure.cpp294 unsigned Reg = P.LiveOutRegs[i]; in initLiveThru() local
343 void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) { in pushRegUnits()
431 void RegPressureTracker::discoverLiveIn(unsigned Reg) { in discoverLiveIn()
442 void RegPressureTracker::discoverLiveOut(unsigned Reg) { in discoverLiveOut()
501 unsigned Reg = RegOpers.Defs[i]; in recede() local
526 unsigned Reg = RegOpers.Uses[i]; in recede() local
545 unsigned Reg = RegOpers.Defs[i]; in recede() local
581 unsigned Reg = RegOpers.Uses[i]; in advance() local
606 unsigned Reg = RegOpers.Defs[i]; in advance() local
721 unsigned Reg = RegOpers.Defs[i]; in bumpUpwardPressure() local
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DMachineLICM.cpp437 unsigned Reg = MO.getReg(); in ProcessMI() local
523 unsigned Reg = *I; in HoistRegionPostRA() local
544 unsigned Reg = MO.getReg(); in HoistRegionPostRA() local
573 unsigned Reg = MO.getReg(); in HoistRegionPostRA() local
590 void MachineLICM::AddToLiveIns(unsigned Reg) { in AddToLiveIns()
784 unsigned Reg, unsigned OpIdx, in getRegisterClassIDAndCost()
821 unsigned Reg = MO.getReg(); in InitRegPressure() local
853 unsigned Reg = MO.getReg(); in UpdateRegPressure() local
872 unsigned Reg = Defs.pop_back_val(); in UpdateRegPressure() local
932 unsigned Reg = MO.getReg(); in IsLoopInvariantInst() local
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/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { in isARMArea1Register()
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { in isARMArea2Register()
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { in isARMArea3Register()
75 static inline bool isCalleeSavedRegister(unsigned Reg, in isCalleeSavedRegister()
/external/llvm/lib/Target/Hexagon/
DHexagonCallingConvLower.h72 bool isAllocated(unsigned Reg) const { in isAllocated()
119 unsigned AllocateReg(unsigned Reg) { in AllocateReg()
126 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg()
142 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg() local
155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg() local
DHexagonVarargsCallingConvention.h56 if (unsigned Reg = State.AllocateReg(RegList1, 6)) { in CC_Hexagon32_VarArgs() local
68 if (unsigned Reg = State.AllocateReg(RegList2, 3)) { in CC_Hexagon32_VarArgs() local
112 if (unsigned Reg = State.AllocateReg(RegList1, 6)) { in RetCC_Hexagon32_VarArgs() local
124 if (unsigned Reg = State.AllocateReg(RegList2, 3)) { in RetCC_Hexagon32_VarArgs() local
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.h57 inline unsigned getRegAsGR64(unsigned Reg) { in getRegAsGR64()
62 inline unsigned getRegAsGR32(unsigned Reg) { in getRegAsGR32()
67 inline unsigned getRegAsGRH32(unsigned Reg) { in getRegAsGRH32()
/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp136 unsigned Reg, in inferRegClassFromUses()
162 unsigned Reg, in inferRegClassFromDef()
223 unsigned Reg = MI.getOperand(i).getReg(); in runOnMachineFunction() local
228 unsigned Reg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
241 unsigned Reg = MI.getOperand(i).getReg(); in runOnMachineFunction() local
/external/llvm/lib/Target/Mips/
DMipsOptimizePICCall.cpp118 static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { in getRegTy()
148 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64; in eraseGPOpnd() local
214 unsigned Reg; in visitNode() local
246 bool OptimizePICCall::isCallViaRegister(MachineInstr &MI, unsigned &Reg, in isCallViaRegister()
288 unsigned Reg = ScopedHT.lookup(Entry).second; in getReg() local
293 void OptimizePICCall::incCntAndSetReg(ValueType Entry, unsigned Reg) { in incCntAndSetReg()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h76 bool contains(unsigned Reg) const { in contains()
260 static bool isStackSlot(unsigned Reg) { in isStackSlot()
266 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index()
280 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister()
287 static bool isVirtualRegister(unsigned Reg) { in isVirtualRegister()
294 static unsigned virtReg2Index(unsigned Reg) { in virtReg2Index()
411 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit()
457 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
670 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, in UpdateRegAllocHint()
729 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, in hasReservedSpillSlot()
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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp860 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass() local
871 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass() local
900 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass() local
912 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass() local
924 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); in DecodeFGRH32RegisterClass() local
935 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass() local
946 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass() local
957 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); in DecodeFGRCCRegisterClass() local
967 unsigned Reg = fieldFromInstruction(Insn, 16, 5); in DecodeMem() local
987 unsigned Reg = fieldFromInstruction(Insn, 6, 5); in DecodeMSA128Mem() local
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/external/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp97 unsigned Reg = CSRegs[I]; in processFunctionBeforeCalleeSavedScan() local
140 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
161 unsigned Reg = SystemZ::ArgGPRs[FirstGPR]; in spillCalleeSavedRegisters() local
186 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
199 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
226 unsigned Reg = CSI[I].getReg(); in restoreCalleeSavedRegisters() local
256 unsigned Reg = CSI[I].getReg(); in restoreCalleeSavedRegisters() local
285 unsigned Reg, int64_t NumBytes, in emitIncrement()
335 unsigned Reg = Save.getReg(); in emitPrologue() local
382 unsigned Reg = Save.getReg(); in emitPrologue() local
/external/llvm/lib/MC/
DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg()
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
/external/compiler-rt/lib/asan/tests/
Dasan_asm_test.cc34 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \ argument
44 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \ argument
67 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \ argument
77 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \ argument
/external/llvm/lib/Target/Sparc/
DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } in setGlobalBaseReg()
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } in setSRetReturnReg()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp63 unsigned Reg, unsigned FrameReg, int Offset ) { in InsertFPImmInst()
94 unsigned Reg, unsigned FrameReg, in InsertFPConstInst()
130 unsigned Reg, int Offset) { in InsertSPImmInst()
163 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst()
305 unsigned Reg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local

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