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Searched defs:VT (Results 1 – 25 of 134) sorted by relevance

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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp65 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
86 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask()
102 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask()
118 void DecodePSHUFLWMask(MVT VT, unsigned Imm, in DecodePSHUFLWMask()
137 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeSHUFPMask()
159 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeUNPCKHMask()
179 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeUNPCKLMask()
196 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm, in DecodeVPERM2X128Mask()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp119 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
131 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
155 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in EmitLoad()
202 MVT VT = CEVT.getSimpleVT(); in TargetMaterializeConstant() local
214 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr, in EmitStore()
249 MVT VT; in SelectLoad() local
274 MVT VT; in SelectStore() local
322 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { in MaterializeFP()
342 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) { in MaterializeGV()
357 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) { in MaterializeInt()
DMipsSEISelLowering.h45 EVT VT) const override { in isShuffleMaskLegal()
/external/llvm/include/llvm/Target/
DTargetLowering.h190 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
314 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
327 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
334 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
341 bool isTypeLegal(EVT VT) const { in isTypeLegal()
357 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
361 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
375 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { in getTypeAction()
378 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
388 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { in getTypeToTransformTo()
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp359 MVT VT = Op.getSimpleValueType(); in Promote() local
381 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
417 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
667 EVT VT = Op.getValueType(); in ExpandSELECT() local
721 EVT VT = Op.getValueType(); in ExpandSEXTINREG() local
744 EVT VT = Op.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
767 EVT VT = Op.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
791 EVT VT = Op.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
820 EVT VT = Op.getValueType(); in ExpandBSWAP() local
851 EVT VT = Mask.getValueType(); in ExpandVSELECT() local
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DSelectionDAG.cpp77 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
730 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
849 EVT VT = N->getValueType(0); in VerifyNodeCommon() local
997 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtOrTrunc()
1003 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getSExtOrTrunc()
1009 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getZExtOrTrunc()
1015 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, in getBoolExtOrTrunc()
1024 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) { in getZeroExtendInReg()
1036 SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtendVectorInReg()
1046 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getSignExtendVectorInReg()
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DDAGCombiner.cpp379 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
674 EVT VT = N0.getValueType(); in ReassociateOps() local
812 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
904 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
962 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1006 EVT VT = Op.getValueType(); in PromoteExtend() local
1035 EVT VT = Op.getValueType(); in PromoteLoad() local
1462 EVT VT = N0.getValueType(); in combineShlAddConstant() local
1486 EVT VT = N0.getValueType(); in visitADD() local
1658 EVT VT = N0.getValueType(); in visitADDC() local
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DLegalizeDAG.cpp189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, in ShuffleWithNarrowerEltType()
263 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
313 EVT VT = Val.getValueType(); in ExpandUnalignedStore() local
436 EVT VT = LD->getValueType(0); in ExpandUnalignedLoad() local
592 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory() local
727 MVT VT = Value.getSimpleValueType(); in LegalizeStoreOps() local
888 MVT VT = Node->getSimpleValueType(0); in LegalizeLoadOps() local
1499 EVT VT = Node->getValueType(0); in ExpandVectorBuildThroughStack() local
1611 EVT VT = Node->getValueType(0); in ExpandDYNAMIC_STACKALLOC() local
1659 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, in LegalizeSetCCCondCode()
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DLegalizeTypes.h66 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction()
71 bool isTypeLegal(EVT VT) const { in isTypeLegal()
75 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
DResourcePriorityQueue.cpp98 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
136 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
336 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
345 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
488 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
499 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp90 MVT VT = Outs[i].VT; in CheckReturn() local
104 MVT VT = Outs[i].VT; in AnalyzeReturn() local
158 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
172 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { in getEquivalentLoadRegType()
246 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
287 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
333 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
603 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
611 EVT VT = EVT::getEVT(CFP->getType()); in LowerConstantInitializer() local
641 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy)) in LowerConstantInitializer() local
660 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
759 EVT VT = Op.getValueType(); in LowerEXTRACT_SUBVECTOR() local
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/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp881 EVT VT = N->getValueType(0); in SelectTable() local
903 EVT VT = LD->getMemoryVT(); in SelectIndexedLoad() local
993 EVT VT = N->getValueType(0); in SelectLoad() local
1017 EVT VT = N->getValueType(0); in SelectPostLoad() local
1052 EVT VT = N->getOperand(2)->getValueType(0); in SelectStore() local
1071 EVT VT = N->getOperand(2)->getValueType(0); in SelectPostStore() local
1100 EVT VT = V64Reg.getValueType(); in operator ()() local
1115 EVT VT = V128Reg.getValueType(); in NarrowVector() local
1127 EVT VT = N->getValueType(0); in SelectLoadLane() local
1172 EVT VT = N->getValueType(0); in SelectPostLoadLane() local
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DAArch64ISelLowering.cpp441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; in AArch64TargetLowering() local
481 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { in addTypeForNEON()
549 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
554 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
590 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); in computeKnownBitsForTargetNode() local
610 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); in computeKnownBitsForTargetNode() local
979 EVT VT = LHS.getValueType(); in emitComparison() local
1023 EVT VT = RHS.getValueType(); in getAArch64Cmp() local
1266 EVT VT = Op.getValueType(); in LowerADDC_ADDE_SUBC_SUBE() local
1390 EVT VT = Op.getValueType(); in LowerVectorFP_TO_INT() local
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp89 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
148 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
153 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
403 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; in ARMTargetLowering() local
1110 EVT VT = N->getValueType(i); in getSchedulingPreference() local
3287 EVT VT = Op.getValueType(); in LowerXALUO() local
3314 EVT VT = Op.getValueType(); in LowerSELECT() local
3347 EVT VT = Op.getValueType(); in LowerSELECT() local
3423 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
3517 EVT VT = Op.getValueType(); in canChangeToInt() local
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/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); in LowerOperation() local
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
377 EVT VT = Op.getValueType(); in LowerROTL() local
390 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
154 EVT VT = Op.getValueType(); in LowerIntrinsicIABS() local
167 EVT VT = Op.getValueType(); in LowerIntrinsicLRP() local
184 EVT VT = Op.getValueType(); in LowerUDIVREM() local
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
154 EVT VT = Op.getValueType(); in LowerIntrinsicIABS() local
167 EVT VT = Op.getValueType(); in LowerIntrinsicLRP() local
184 EVT VT = Op.getValueType(); in LowerUDIVREM() local
DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); in LowerOperation() local
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
377 EVT VT = Op.getValueType(); in LowerROTL() local
390 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp81 EVT VT = Vec.getValueType(); in ExtractSubVector() local
140 EVT VT = Vec.getValueType(); in InsertSubVector() local
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, in Concat128BitVectors()
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, in Concat256BitVectors()
434 MVT VT = IntVTs[i]; in resetOperationActions() local
603 MVT VT = IntVTs[i]; in resetOperationActions() local
806 MVT VT = (MVT::SimpleValueType)i; in resetOperationActions() local
986 MVT VT = (MVT::SimpleValueType)i; in resetOperationActions() local
1012 MVT VT = (MVT::SimpleValueType)i; in resetOperationActions() local
1287 MVT VT = (MVT::SimpleValueType)i; in resetOperationActions() local
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DX86FastISel.cpp336 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
364 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, in X86FastEmitLoad()
425 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore()
486 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
940 MVT VT; in X86SelectStore() local
1096 MVT VT; in X86SelectLoad() local
1114 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1135 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1152 EVT VT) { in X86FastEmitCompare()
1187 MVT VT; in X86SelectCmp() local
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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h449 bool bitsGT(MVT VT) const { in bitsGT()
454 bool bitsGE(MVT VT) const { in bitsGE()
459 bool bitsLT(MVT VT) const { in bitsLT()
464 bool bitsLE(MVT VT) const { in bitsLE()
505 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
/external/llvm/lib/Target/Hexagon/
DHexagonCallingConvLower.cpp117 EVT VT = Outs[i].VT; in AnalyzeReturn() local
185 EVT VT = Ins[i].VT; in AnalyzeCallResult() local
197 void Hexagon_CCState::AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn) { in AnalyzeCallResult()
/external/llvm/lib/IR/
DValueTypes.cpp29 EVT VT; in getExtendedIntegerVT() local
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, in getExtendedVectorVT()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp255 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
269 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
396 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, in PPCSimplifyAddress()
427 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad()
544 MVT VT; in SelectLoad() local
568 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore()
661 MVT VT; in SelectStore() local
991 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, in PPCMoveToIntReg()
1813 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { in PPCMaterializeFP()
1864 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { in PPCMaterializeGV()
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