Home
last modified time | relevance | path

Searched refs:ANY_EXTEND (Results 1 – 25 of 35) sorted by relevance

12

/external/llvm/test/CodeGen/AArch64/
Darm64-AnInfiniteLoopInDAGCombine.ll10 ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp97 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
260 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
274 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
288 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
306 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), in PromoteIntRes_BUILD_PAIR()
434 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); in PromoteIntRes_INT_EXTEND()
804 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; in PromoteIntegerOperand()
889 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op); in PromoteIntOp_ANY_EXTEND()
1054 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); in PromoteIntOp_SIGN_EXTEND()
[all …]
DTargetLowering.cpp357 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, in ShrinkDemandedOp()
639 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { in SimplifyDemandedBits()
653 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), in SimplifyDemandedBits()
675 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, in SimplifyDemandedBits()
888 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
910 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
942 case ISD::ANY_EXTEND: { in SimplifyDemandedBits()
1534 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
DDAGCombiner.cpp861 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
863 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); in PromoteOperand()
1236 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
1313 case ISD::ANY_EXTEND: in combine()
2461 (N0.getOpcode() == ISD::ANY_EXTEND && in SimplifyBinOpWithSameOpcodeHands()
2643 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
2876 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
2878 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; in visitAND()
3672 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
3676 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
[all …]
DLegalizeVectorTypes.cpp69 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
407 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
482 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
617 case ISD::ANY_EXTEND: in SplitVectorResult()
1222 case ISD::ANY_EXTEND: in SplitVectorOperand()
1605 case ISD::ANY_EXTEND: in WidenVectorResult()
2404 case ISD::ANY_EXTEND: in WidenVectorOperand()
2489 case ISD::ANY_EXTEND: in WidenVecOp_EXTEND()
DSelectionDAGBuilder.cpp158 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
200 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); in getCopyFromParts()
311 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyFromPartsVector()
332 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyFromPartsVector()
349 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { in getCopyToParts()
512 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyToPartsVector()
522 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), in getCopyToPartsVector()
776 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; in getCopyToRegs()
1234 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in visitRet()
1244 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) in visitRet()
[all …]
DSelectionDAGDumper.cpp222 case ISD::ANY_EXTEND: return "any_extend"; in getOperationName()
DLegalizeTypesGeneric.cpp223 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0)); in ExpandRes_EXTRACT_VECTOR_ELT()
DLegalizeDAG.cpp449 ISD::ANY_EXTEND, dl, VT, Result); in ExpandUnalignedLoad()
1105 ISD::FP_EXTEND : ISD::ANY_EXTEND); in LegalizeLoadOps()
3712 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) && in ExpandNode()
3717 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi); in ExpandNode()
3869 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); in ExpandNode()
4232 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4250 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
DSelectionDAG.cpp239 return ISD::ANY_EXTEND; in getExtForLoadExtType()
999 getNode(ISD::ANY_EXTEND, DL, VT, Op) : in getAnyExtOrTrunc()
2200 case ISD::ANY_EXTEND: { in computeKnownBits()
2679 case ISD::ANY_EXTEND: in getNode()
2826 case ISD::ANY_EXTEND: in getNode()
2838 OpOpcode == ISD::ANY_EXTEND) in getNode()
2864 OpOpcode == ISD::ANY_EXTEND) { in getNode()
DLegalizeVectorOps.cpp269 case ISD::ANY_EXTEND: in LegalizeOp()
DLegalizeTypes.cpp1000 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); in JoinIntegers()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h365 ANY_EXTEND, enumerator
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp763 case ISD::ANY_EXTEND: in expandRxSBG()
869 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND) in tryRISBGZero()
927 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND) in tryRxSBG()
DSystemZISelLowering.cpp658 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1775 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result); in lowerSELECT_CC()
1846 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi); in lowerGlobalTLSAddress()
1926 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In); in lowerBITCAST()
2551 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT, in PerformDAGCombine()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp720 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
948 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal); in LowerCall()
1530 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
1789 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P); in LowerFormalArguments()
1814 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); in LowerFormalArguments()
1815 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1); in LowerFormalArguments()
1858 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt); in LowerFormalArguments()
2089 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal); in LowerReturn()
2794 if (Val.getOpcode() == ISD::ANY_EXTEND) { in PerformANDCombine()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp185 setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
200 setOperationAction(ISD::ANY_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp185 setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
200 setOperationAction(ISD::ANY_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp618 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1020 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), in LowerSIGN_EXTEND()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1281 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
1292 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp651 setTargetDAGCombine(ISD::ANY_EXTEND); in PPCTargetLowering()
4785 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
7449 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND) in DAGCombineTruncBoolExt()
7461 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND) in DAGCombineTruncBoolExt()
7471 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) && in DAGCombineTruncBoolExt()
7502 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) && in DAGCombineTruncBoolExt()
7514 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) { in DAGCombineTruncBoolExt()
7600 PromOp.getOpcode() == ISD::ANY_EXTEND) { in DAGCombineTruncBoolExt()
7787 if (N->getOpcode() != ISD::ANY_EXTEND) { in DAGCombineExtBoolTrunc()
7933 case ISD::ANY_EXTEND: in PerformDAGCombine()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp872 setOperationAction(ISD::ANY_EXTEND, VT, Expand); in resetOperationActions()
1218 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom); in resetOperationActions()
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1575 setTargetDAGCombine(ISD::ANY_EXTEND); in resetOperationActions()
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
9934 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); in LowerINSERT_VECTOR_ELT_SSE4()
10040 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); in LowerINSERT_VECTOR_ELT()
10070 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); in LowerSCALAR_TO_VECTOR()
[all …]
DX86ISelDAGToDAG.cpp925 if (X.getOpcode() == ISD::ANY_EXTEND) { in FoldMaskAndShiftToScale()
1161 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in MatchAddressRecursively()
/external/llvm/include/llvm/Target/
DTargetLowering.h128 return ISD::ANY_EXTEND; in getExtendForContent()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
767 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
1114 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()

12