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Searched refs:CR0_PG_MASK (Results 1 – 5 of 5) sorted by relevance

/external/qemu/target-i386/
Dhelper.c863 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != in cpu_x86_update_cr0()
864 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { in cpu_x86_update_cr0()
869 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) && in cpu_x86_update_cr0()
877 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) && in cpu_x86_update_cr0()
902 if (env->cr[0] & CR0_PG_MASK) { in cpu_x86_update_cr3()
981 if (!(env->cr[0] & CR0_PG_MASK)) { in cpu_x86_handle_mmu_fault()
1319 if (!(env->cr[0] & CR0_PG_MASK)) { in cpu_get_phys_page_debug()
Dsmm_helper.c170 env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK)); in do_smm_enter()
Dcpu.h206 #define CR0_PG_MASK (1 << 31) macro
Dhax-all.c46 return !(env->cr[0] & CR0_PG_MASK); in hax_vcpu_emulation_mode()
Dseg_helper.c341 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { in switch_tss()