| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 763 enum CondCode { enum
796 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
802 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
809 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
817 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
823 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
827 CondCode getSetCCSwappedOperands(CondCode Operation);
833 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
839 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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| D | Analysis.h | 72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 38 enum CondCode { enum
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 32 enum CondCode { enum
63 unsigned GetCondBranchFromCond(CondCode CC);
67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
75 CondCode getCondFromCMovOpc(unsigned Opc);
79 CondCode GetOppositeBranchCondition(CondCode CC);
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc) in reverseCondCode()
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); in reverseCondCode()
33 static inline CondCode inverseCondCode(CondCode cc) in inverseCondCode()
35 return static_cast<CondCode>(cc ^ 7); in inverseCondCode()
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| D | nv50_ir.h | 168 enum CondCode enum
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; } in setCondition()
827 CondCode getCondition() const { return setCond; } in getCondition()
830 CondCode setCond;
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| D | nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc) in reverseCondCode()
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); in reverseCondCode()
33 static inline CondCode inverseCondCode(CondCode cc) in inverseCondCode()
35 return static_cast<CondCode>(cc ^ 7); in inverseCondCode()
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| D | nv50_ir.h | 168 enum CondCode enum
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; } in setCondition()
827 CondCode getCondition() const { return setCond; } in getCondition()
830 CondCode setCond;
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| D | nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.h | 33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
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| D | MipsInstPrinter.cpp | 37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
247 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 503 class CondCode; // ISD::CondCode enums
504 def SETOEQ : CondCode; def SETOGT : CondCode;
505 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
506 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
507 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
508 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
510 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
511 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
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| D | TargetLowering.h | 589 getCondCodeAction(ISD::CondCode CC, MVT VT) const { in getCondCodeAction()
602 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { in isCondCodeLegal()
1156 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1431 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1437 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
1781 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1919 ISD::CondCode &CCCode, SDLoc DL) const;
2032 ISD::CondCode Cond, bool foldBooleans,
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 192 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
213 inline static const char *getCondCodeName(CondCode Code) { in getCondCodeName()
235 inline static CondCode getInvertedCondCode(CondCode Code) { in getInvertedCondCode()
238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in getNZCVToSatisfyCondCode()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 151 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
173 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
188 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionalCompares.cpp | 165 AArch64CC::CondCode HeadCmpBBCC;
171 AArch64CC::CondCode CmpBBTailCC;
272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
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| D | AArch64ISelLowering.cpp | 786 unsigned CondCode = MI->getOperand(3).getImm(); in EmitF128CSEL() local
799 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); in EmitF128CSEL()
851 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { in changeIntCCToAArch64CC()
879 static void changeFPCCToAArch64CC(ISD::CondCode CC, in changeFPCCToAArch64CC()
880 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC() argument
881 AArch64CC::CondCode &CondCode2) { in changeFPCCToAArch64CC()
888 CondCode = AArch64CC::EQ; in changeFPCCToAArch64CC()
892 CondCode = AArch64CC::GT; in changeFPCCToAArch64CC()
896 CondCode = AArch64CC::GE; in changeFPCCToAArch64CC()
899 CondCode = AArch64CC::MI; in changeFPCCToAArch64CC()
[all …]
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| D | AArch64BranchRelaxation.cpp | 346 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm(); in invertBccCondition()
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| D | AArch64InstrInfo.cpp | 188 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in ReverseBranchCondition()
418 AArch64CC::CondCode CC; in insertSelect()
423 CC = AArch64CC::CondCode(Cond[0].getImm()); in insertSelect()
840 AArch64CC::CondCode CC; in optimizeCompareInstr()
845 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm(); in optimizeCompareInstr()
857 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 263 const ISD::CondCode Cond; in ARMTargetLowering()
1139 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { in IntCCToARMCC()
1156 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC() argument
1162 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
1164 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
1166 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
1167 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
1168 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
1169 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1170 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 121 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
493 ISD::CondCode CC, SDLoc dl) { in SelectCC()
590 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { in getPredicateForSetCC()
621 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { in getCRIdxForSetCC()
653 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC, in getVCmpInst()
747 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SelectSETCC()
1267 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in Select()
1409 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in Select()
1432 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
1433 SDValue Ops[] = { getI32Imm(PCC), CondCode, in Select()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 60 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
198 AArch64CC::CondCode Code;
242 struct CondCodeOp CondCode; member
274 CondCode = o.CondCode; in AArch64Operand()
336 AArch64CC::CondCode getCondCode() const { in getCondCode()
338 return CondCode.Code; in getCondCode()
1641 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateCondCode()
1643 Op->CondCode.Code = Code; in CreateCondCode()
2224 AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) { in parseCondCodeString()
2225 AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower()) in parseCondCodeString()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.h | 174 unsigned CondCode = 0) const;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 670 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in SoftenFloatOp_BR_CC()
716 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in SoftenFloatOp_SELECT_CC()
739 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SoftenFloatOp_SETCC()
1310 ISD::CondCode &CCCode, in FloatExpandSetCCOperands()
1340 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in ExpandFloatOp_BR_CC()
1433 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in ExpandFloatOp_SELECT_CC()
1451 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in ExpandFloatOp_SETCC()
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