| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 164 const MachineInstr *Def; member in __anon2f08fc220111::ValueTracker
215 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
217 assert(Def->getOperand(DefIdx).isDef() && in ValueTracker()
218 Def->getOperand(DefIdx).isReg() && in ValueTracker()
221 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
538 unsigned Def = MODef.getReg(); in optimizeCopyOrBitcast() local
540 if (TargetRegisterInfo::isPhysicalRegister(Def)) in optimizeCopyOrBitcast()
543 const TargetRegisterClass *DefRC = MRI->getRegClass(Def); in optimizeCopyOrBitcast()
581 unsigned NewVR = TargetRegisterInfo::isPhysicalRegister(Def) ? Def : in optimizeCopyOrBitcast()
588 MRI->replaceRegWith(Def, NewVR); in optimizeCopyOrBitcast()
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| D | MachineCopyPropagation.cpp | 114 static bool isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, in isNopCopy() argument
117 if (Def == SrcSrc) in isNopCopy()
119 if (TRI->isSubRegister(SrcSrc, Def)) { in isNopCopy()
121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy()
151 unsigned Def = MI->getOperand(0).getReg(); in CopyPropagateBlock() local
154 if (TargetRegisterInfo::isVirtualRegister(Def) || in CopyPropagateBlock()
162 if (!MRI->isReserved(Def) && in CopyPropagateBlock()
164 isNopCopy(CopyMI, Def, Src, TRI)) { in CopyPropagateBlock()
184 I->clearRegisterKills(Def, TRI); in CopyPropagateBlock()
214 SourceNoLongerAvailable(Def, SrcMap, AvailCopyMap); in CopyPropagateBlock()
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| D | LiveVariables.cpp | 199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef() local
200 if (!Def) in FindLastPartialDef()
202 unsigned Dist = DistanceMap[Def]; in FindLastPartialDef()
205 LastDef = Def; in FindLastPartialDef()
292 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastRefOrPartRef() local
293 if (Def && Def != LastDef) { in FindLastRefOrPartRef()
296 unsigned Dist = DistanceMap[Def]; in FindLastRefOrPartRef()
341 MachineInstr *Def = PhysRegDef[SubReg]; in HandlePhysRegKill() local
342 if (Def && Def != LastDef) { in HandlePhysRegKill()
345 unsigned Dist = DistanceMap[Def]; in HandlePhysRegKill()
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| D | LiveInterval.cpp | 52 VNInfo *LiveRange::createDeadDef(SlotIndex Def, in createDeadDef() argument
54 assert(!Def.isDead() && "Cannot define a value at the dead slot"); in createDeadDef()
55 iterator I = find(Def); in createDeadDef()
57 VNInfo *VNI = getNextValue(Def, VNInfoAllocator); in createDeadDef()
58 segments.push_back(Segment(Def, Def.getDeadSlot(), VNI)); in createDeadDef()
61 if (SlotIndex::isSameInstr(Def, I->start)) { in createDeadDef()
69 Def = std::min(Def, I->start); in createDeadDef()
70 if (Def != I->start) in createDeadDef()
71 I->start = I->valno->def = Def; in createDeadDef()
74 assert(SlotIndex::isEarlierInstr(Def, I->start) && "Already live at def"); in createDeadDef()
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| D | ExecutionDepsFix.cpp | 121 int Def; member
365 LiveRegs[rx].Def = -(1 << 20); in enterBasicBlock()
378 LiveRegs[rx].Def = -1; in enterBasicBlock()
396 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def); in enterBasicBlock()
436 LiveRegs[i].Def -= CurInstr; in leaveBasicBlock()
473 unsigned Clearance = CurInstr - LiveRegs[rx].Def; in shouldBreakDependence()
531 LiveRegs[rx].Def = CurInstr; in processDefs()
657 if (LR.Def < i->Def) { in visitSoftInstr()
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| D | SplitKit.cpp | 396 SlotIndex Def = OldVNI->def; in defValue() local
397 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), OldVNI)); in defValue()
403 SlotIndex Def = VNI->def; in defValue() local
404 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI)); in defValue()
423 SlotIndex Def = VNI->def; in forceRecompute() local
425 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI)); in forceRecompute()
436 SlotIndex Def; in defFromParent() local
446 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late); in defFromParent()
452 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late) in defFromParent()
458 return defValue(RegIdx, ParentVNI, Def); in defFromParent()
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| D | MachineLICM.cpp | 155 unsigned Def; member
158 : MI(mi), Def(def), FI(fi) {} in CandidateInfo()
168 void HoistPostRA(MachineInstr *MI, unsigned Def);
414 unsigned Def = 0; in ProcessMI() local
464 if (Def) in ProcessMI()
467 Def = Reg; in ProcessMI()
485 if (Def && !RuledOut) { in ProcessMI()
489 Candidates.push_back(CandidateInfo(MI, Def, FI)); in ProcessMI()
565 unsigned Def = Candidates[i].Def; in HoistRegionPostRA() local
566 if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) { in HoistRegionPostRA()
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| /external/llvm/lib/IR/ |
| D | Dominators.cpp | 80 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
83 const BasicBlock *DefBB = Def->getParent(); in dominates()
94 if (Def == User) in dominates()
101 if (isa<InvokeInst>(Def) || isa<PHINode>(User)) in dominates()
102 return dominates(Def, UseBB); in dominates()
109 for (; &*I != Def && &*I != User; ++I) in dominates()
112 return &*I == Def; in dominates()
117 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
119 const BasicBlock *DefBB = Def->getParent(); in dominates()
132 const InvokeInst *II = dyn_cast<InvokeInst>(Def); in dominates()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 506 static bool canDefBePartOfLOH(const MachineInstr *Def) { in canDefBePartOfLOH() argument
507 unsigned Opc = Def->getOpcode(); in canDefBePartOfLOH()
516 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
527 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
581 const MachineInstr *Def = DefsIt.first; in reachedUsesToDefs() local
585 if ((ADRPMode && Def->getOpcode() != AArch64::ADRP) || in reachedUsesToDefs()
586 (!ADRPMode && !canDefBePartOfLOH(Def)) || in reachedUsesToDefs()
707 const MachineInstr *Def = *UseToDefs.find(Instr)->second.begin(); in isCandidate() local
708 if (Def->getOpcode() != AArch64::ADRP) { in isCandidate()
715 if (!MDT->dominates(Def, Instr)) in isCandidate()
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| D | AArch64AdvSIMDScalarPass.cpp | 199 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
201 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
202 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
212 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
214 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
215 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
292 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction() local
294 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
295 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
300 Def->eraseFromParent(); in transformInstruction()
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| /external/clang/lib/Lex/ |
| D | MacroInfo.cpp | 155 for (DefInfo Def = getDefinition(); Def; Def = Def.getPreviousDefinition()) { in findDirectiveAtLoc() local
156 if (Def.getLocation().isInvalid() || // For macros defined on the command line. in findDirectiveAtLoc()
157 SM.isBeforeInTranslationUnit(Def.getLocation(), L)) in findDirectiveAtLoc()
158 return (!Def.isUndefined() || in findDirectiveAtLoc()
159 SM.isBeforeInTranslationUnit(L, Def.getUndefLocation())) in findDirectiveAtLoc()
160 ? Def : DefInfo(); in findDirectiveAtLoc()
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| D | PreprocessingRecord.cpp | 323 MacroDefinition *Def) { in RegisterMacroDefinition() argument
324 MacroDefinitions[Macro] = Def; in RegisterMacroDefinition()
379 else if (MacroDefinition *Def = findMacroDefinition(MI)) in addMacroExpansion() local
381 new (*this) MacroExpansion(Def, Range)); in addMacroExpansion()
423 MacroDefinition *Def in MacroDefined() local
425 addPreprocessedEntity(Def); in MacroDefined()
426 MacroDefinitions[MI] = Def; in MacroDefined()
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRLiveRanges.cpp | 91 for (const MachineOperand &Def : MI.operands()) { in runOnMachineFunction() local
92 if (!Def.isReg() || !Def.isDef() ||!TargetRegisterInfo::isVirtualRegister(Def.getReg())) in runOnMachineFunction()
95 const TargetRegisterClass *RC = MRI.getRegClass(Def.getReg()); in runOnMachineFunction()
99 LiveInterval &LI = LIS->getInterval(Def.getReg()); in runOnMachineFunction()
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| D | R600EmitClauseMarkers.cpp | 182 MachineBasicBlock::iterator Def, in canClauseLocalKillFitInClause() argument
186 MOI = Def->operands_begin(), in canClauseLocalKillFitInClause()
187 MOE = Def->operands_end(); MOI != MOE; ++MOI) { in canClauseLocalKillFitInClause()
195 for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) { in canClauseLocalKillFitInClause()
215 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1) in canClauseLocalKillFitInClause()
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| D | SIFixSGPRCopies.cpp | 168 MachineInstr *Def = MRI.getVRegDef(Reg); in inferRegClassFromDef() local
169 if (Def->getOpcode() != AMDGPU::COPY) { in inferRegClassFromDef()
173 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(), in inferRegClassFromDef()
174 Def->getOperand(1).getSubReg()); in inferRegClassFromDef()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 61 CodeGenSchedRW(unsigned Idx, Record *Def) in CodeGenSchedRW()
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { in CodeGenSchedRW()
63 Name = Def->getName(); in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
65 HasVariants = Def->isSubClassOf("SchedVariant"); in CodeGenSchedRW()
67 IsVariadic = Def->getValueAsBit("Variadic"); in CodeGenSchedRW()
72 IsSequence = Def->isSubClassOf("WriteSequence"); in CodeGenSchedRW()
324 CodeGenSchedRW &getSchedRW(Record *Def) { in getSchedRW() argument
325 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW()
326 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
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| D | DAGISelMatcherGen.cpp | 623 Record *Def = DI->getDef(); in EmitResultLeafAsOperand() local
624 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
626 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
632 if (Def->getName() == "zero_reg") { in EmitResultLeafAsOperand()
640 if (Def->isSubClassOf("RegisterOperand")) in EmitResultLeafAsOperand()
641 Def = Def->getValueAsDef("RegClass"); in EmitResultLeafAsOperand()
642 if (Def->isSubClassOf("RegisterClass")) { in EmitResultLeafAsOperand()
643 std::string Value = getQualifiedName(Def) + "RegClassID"; in EmitResultLeafAsOperand()
650 if (Def->isSubClassOf("SubRegIndex")) { in EmitResultLeafAsOperand()
651 std::string Value = getQualifiedName(Def); in EmitResultLeafAsOperand()
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| /external/clang/test/Modules/ |
| D | decldef.m | 7 @class Def;
8 Def *def;
12 A *a1; // expected-error{{declaration of 'A' must be imported from module 'decldef.Def' before it i…
23 …// expected-error@-2{{definition of 'A' must be imported from module 'decldef.Def' before it is re…
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| D | decldef.mm | 11 @class Def;
12 Def *def;
24 A *a1; // expected-error{{declaration of 'A' must be imported from module 'decldef.Def'}}
37 …// expected-error@-2{{definition of 'A' must be imported from module 'decldef.Def' before it is re…
47 …// expected-error@-2{{definition of 'B' must be imported from module 'decldef.Def' before it is re…
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 204 MachineInstr *Def = Op->getParent(); in eraseInstrWithNoUses() local
208 if (DeadInstr.find(Def) != DeadInstr.end()) in eraseInstrWithNoUses()
215 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) { in eraseInstrWithNoUses()
216 MachineOperand &MODef = Def->getOperand(j); in eraseInstrWithNoUses()
228 if (&*II == Def) in eraseInstrWithNoUses()
239 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); in eraseInstrWithNoUses()
240 DeadInstr.insert(Def); in eraseInstrWithNoUses()
309 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() local
310 if (!Def) in optimizeSDPattern()
312 if (Def->isImplicitDef()) in optimizeSDPattern()
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 1964 for (auto *Def : Defs) { in genBuiltinsDef() local
1965 if (Def->hasBody()) in genBuiltinsDef()
1969 if (Def->hasSplat()) in genBuiltinsDef()
1972 std::string S = "BUILTIN(__builtin_neon_" + Def->getMangledName() + ", \""; in genBuiltinsDef()
1974 S += Def->getBuiltinTypeStr(); in genBuiltinsDef()
2002 for (auto *Def : Defs) { in genOverloadTypeCheckCode() local
2005 if (Def->hasBody()) in genOverloadTypeCheckCode()
2009 if (Def->hasSplat()) in genOverloadTypeCheckCode()
2013 if (Def->protoHasScalar()) in genOverloadTypeCheckCode()
2017 Type Ty = Def->getReturnType(); in genOverloadTypeCheckCode()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 40 : Def(false), Use(false), IndirectDef(false), IndirectUse(false) {} in Reference()
43 Def |= Other.Def; in operator |=()
50 operator bool() const { return Def || Use; } in operator bool()
54 bool Def; member
151 Ref.Def = true; in getRegReferences()
347 (!CCRefs.Def && adjustCCMasksForInstr(MI, Compare, CCUsers))) { in optimizeCompareZero()
353 if (SrcRefs.Def) in optimizeCompareZero()
356 if (CCRefs.Use && CCRefs.Def) in optimizeCompareZero()
450 if (CCRefs.Def) { in processBlock()
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| /external/valgrind/main/memcheck/tests/ |
| D | origin1-yes.stderr.exp | 57 Def 1 of 3
59 Def 2 of 3
61 Def 3 of 3
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| /external/llvm/include/llvm/IR/ |
| D | Dominators.h | 94 bool dominates(const Instruction *Def, const Use &U) const;
95 bool dominates(const Instruction *Def, const Instruction *User) const;
96 bool dominates(const Instruction *Def, const BasicBlock *BB) const;
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| /external/clang/lib/Serialization/ |
| D | ASTCommon.cpp | 103 if (const TagDecl *Def = cast<TagDecl>(DC)->getDefinition()) in getDefinitiveDeclContext() local
104 return Def; in getDefinitiveDeclContext()
131 if (const ObjCProtocolDecl *Def in getDefinitiveDeclContext() local
133 return Def; in getDefinitiveDeclContext()
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