| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 486 FLOG, FLOG2, FLOG10, FEXP, FEXP2, enumerator
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 775 setOperationAction(ISD::FEXP2, MVT::f16, Expand); in initActions()
786 setOperationAction(ISD::FEXP2, MVT::f32, Expand); in initActions()
797 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in initActions()
808 setOperationAction(ISD::FEXP2, MVT::f128, Expand); in initActions()
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| D | BasicTargetTransformInfo.cpp | 559 case Intrinsic::exp2: ISD = ISD::FEXP2; break; in getIntrinsicInstrCost()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 155 case ISD::FEXP2: return "fexp2"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 77 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
822 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorOps.cpp | 286 case ISD::FEXP2: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 80 case ISD::FEXP2: in ScalarizeVectorResult()
595 case ISD::FEXP2: in SplitVectorResult()
1626 case ISD::FEXP2: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3507 case ISD::FEXP2: in ExpandNode()
4307 case ISD::FEXP2: in PromoteNode()
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| D | SelectionDAGBuilder.cpp | 4372 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); in expandExp2()
5984 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 125 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
339 setOperationAction(ISD::FEXP2, VT, Expand); in AMDGPUTargetLowering()
911 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 310 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1851 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsMSAInstrInfo.td | 2082 // 1.0 when we only need to match ISD::FEXP2.
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 377 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 468 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
486 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
503 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 506 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 443 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 799 setOperationAction(ISD::FEXP2, MVT::f80, Expand); in resetOperationActions()
863 setOperationAction(ISD::FEXP2, VT, Expand); in resetOperationActions()
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