| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
113 "FNEG $dst, $src0",
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| D | R600ISelLowering.cpp | 493 DAG.getNode(ISD::FNEG, DL, VT, Cond)); in LowerSELECT_CC()
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| D | AMDILISelLowering.cpp | 539 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq); in LowerSDIV24()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
113 "FNEG $dst, $src0",
|
| D | R600ISelLowering.cpp | 493 DAG.getNode(ISD::FNEG, DL, VT, Cond)); in LowerSELECT_CC()
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| D | AMDILISelLowering.cpp | 539 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq); in LowerSDIV24()
|
| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 102 int FNEG = 118; field
|
| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| D | Opcodes.java | 257 int FNEG = 118; // - field
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| D | Frame.java | 833 case Opcodes.FNEG: in execute()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 485 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
| D | BasicInterpreter.java | 149 case FNEG: in unaryOperation()
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| D | BasicVerifier.java | 122 case FNEG: in unaryOperation()
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| D | Frame.java | 450 case Opcodes.FNEG: in execute()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 85 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
830 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
875 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1039 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1040 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
|
| D | DAGCombiner.cpp | 453 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
515 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
1255 case ISD::FNEG: return visitFNEG(N); in visit()
6254 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
6263 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
6518 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
6523 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
6699 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) in visitFSUB()
6700 return DAG.getNode(ISD::FNEG, dl, VT, N1); in visitFSUB()
6739 DAG.getNode(ISD::FNEG, dl, VT, N1)); in visitFSUB()
[all …]
|
| D | LegalizeVectorOps.cpp | 274 case ISD::FNEG: in LegalizeOp()
654 case ISD::FNEG: in Expand()
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| D | SelectionDAGDumper.cpp | 143 case ISD::FNEG: return "fneg"; in getOperationName()
|
| D | LegalizeDAG.cpp | 1601 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), in ExpandFCOPYSIGN()
3434 case ISD::FNEG: in ExpandNode()
3448 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); in ExpandNode()
3588 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandNode()
3590 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 335 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
338 "FNEG $dst, $src0",
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1174 setOperationAction(ISD::FNEG, MVT::f32, Legal); in HexagonTargetLowering()
1175 setOperationAction(ISD::FNEG, MVT::f64, Expand); in HexagonTargetLowering()
1285 setOperationAction(ISD::FNEG, MVT::f32, Expand); in HexagonTargetLowering()
1286 setOperationAction(ISD::FNEG, MVT::f64, Expand); in HexagonTargetLowering()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1507 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1601 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1604 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1623 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2519 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2638 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
2822 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
|
| /external/vixl/src/a64/ |
| D | constants-a64.h | 944 FNEG = FNEG_s, enumerator
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| D | disasm-a64.cc | 1000 FORMAT(FNEG, "fneg"); in VisitFPDataProcessing1Source()
|
| /external/chromium_org/v8/src/arm64/ |
| D | constants-arm64.h | 1062 FNEG = FNEG_s, enumerator
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| /external/javassist/src/main/javassist/bytecode/analysis/ |
| D | Executor.java | 374 case FNEG: in execute()
|