| /external/valgrind/main/none/tests/ppc64/ |
| D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
899 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1007 case FSQRT: in check_double_guarded_arithmetic_op()
1112 case FSQRT: in check_double_guarded_arithmetic_op()
1181 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/valgrind/main/none/tests/ppc32/ |
| D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
899 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1007 case FSQRT: in check_double_guarded_arithmetic_op()
1112 case FSQRT: in check_double_guarded_arithmetic_op()
1181 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 485 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| /external/llvm/lib/CodeGen/ |
| D | BasicTargetTransformInfo.cpp | 197 return TLI->isTypeLegal(VT) && TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
555 case Intrinsic::sqrt: ISD = ISD::FSQRT; break; in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 270 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
311 Opcode = ISD::FSQRT; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 181 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
438 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
662 setTargetDAGCombine(ISD::FSQRT); in PPCTargetLowering()
7943 if (N->getOperand(1).getOpcode() == ISD::FSQRT) { in PerformDAGCombine()
7952 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) { in PerformDAGCombine()
7965 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) { in PerformDAGCombine()
7989 case ISD::FSQRT: { in PerformDAGCombine()
|
| /external/oprofile/events/ppc64/ibm-compat-v1/ |
| D | events | 28 …FPU_FLOP_GRP2 : (Group 2 pm_compat_utilization2) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
|
| /external/oprofile/events/ppc64/970MP/ |
| D | events | 68 …rs:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
133 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
134 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
228 …:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
468 …zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
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| /external/oprofile/events/ppc64/970/ |
| D | events | 63 …rs:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
128 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
129 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
223 …:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
463 …zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 144 case ISD::FSQRT: return "fsqrt"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 95 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
837 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorOps.cpp | 277 case ISD::FSQRT: in LegalizeOp()
|
| D | LegalizeVectorTypes.cpp | 93 case ISD::FSQRT: in ScalarizeVectorResult()
609 case ISD::FSQRT: in SplitVectorResult()
1636 case ISD::FSQRT: in WidenVectorResult()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 546 // FDIV,FSQRT
548 // TODO: Specialize FSQRT for longer latency.
|
| /external/oprofile/events/ppc64/power6/ |
| D | events | 742 …0 name:PM_FPU0_FSQRT_FDIV_GRP120 : (Group 120 pm_fpu0_flop) FPU0 executed FSQRT or FDIV instruction
746 …:PM_FPU0_FLOP_GRP121 : (Group 121 pm_fpu0_misc) FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
766 …0 name:PM_FPU1_FSQRT_FDIV_GRP124 : (Group 124 pm_fpu1_flop) FPU1 executed FSQRT or FDIV instruction
770 …:PM_FPU1_FLOP_GRP125 : (Group 125 pm_fpu1_misc) FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
790 …1000 name:PM_FPU_FSQRT_FDIV_GRP128 : (Group 128 pm_fpu_flop) FPU executed FSQRT or FDIV instruction
791 …ame:PM_FPU_FLOP_GRP128 : (Group 128 pm_fpu_flop) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
1144 …mum:1000 name:PM_FPU_FSQRT_FDIV_GRP187 : (Group 187 pm_hpm1) FPU executed FSQRT or FDIV instruction
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| /external/oprofile/events/ppc64/power4/ |
| D | events | 163 …:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP15 : (Group 15 pm_fpu1) FPU executed FSQRT instruction
308 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP30 : (Group 30 pm_fpu4) FPU0 executed FSQRT instruction
309 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP30 : (Group 30 pm_fpu4) FPU1 executed FSQRT instruction
553 …:zero minimum:1000 name:PM_FPU_FSQRT_GRP54 : (Group 54 pm_pe_bench1) FPU executed FSQRT instruction
|
| /external/vixl/src/a64/ |
| D | constants-a64.h | 947 FSQRT = FSQRT_s, enumerator
|
| D | disasm-a64.cc | 1001 FORMAT(FSQRT, "fsqrt"); in VisitFPDataProcessing1Source()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1113 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in HexagonTargetLowering()
1114 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in HexagonTargetLowering()
|
| /external/chromium_org/v8/src/arm64/ |
| D | constants-arm64.h | 1065 FSQRT = FSQRT_s, enumerator
|
| D | disasm-arm64.cc | 994 FORMAT(FSQRT, "fsqrt"); in VisitFPDataProcessing1Source()
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| /external/oprofile/events/ppc64/power5++/ |
| D | events | 519 …:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP83 : (Group 83 pm_fpu2) FPU executed FSQRT instruction
536 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU0 executed FSQRT instruction
537 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU1 executed FSQRT instruction
891 …um:zero minimum:1000 name:PM_FPU_FSQRT_GRP145 : (Group 145 pm_fpuX6) FPU executed FSQRT instruction
928 … um:zero minimum:1000 name:PM_FPU_FSQRT_GRP151 : (Group 151 pm_flop) FPU executed FSQRT instruction
|
| /external/oprofile/events/ppc64/power5+/ |
| D | events | 678 …:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP83 : (Group 83 pm_fpu2) FPU executed FSQRT instruction
701 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU0 executed FSQRT instruction
702 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU1 executed FSQRT instruction
1174 …um:zero minimum:1000 name:PM_FPU_FSQRT_GRP145 : (Group 145 pm_fpuX6) FPU executed FSQRT instruction
1223 … um:zero minimum:1000 name:PM_FPU_FSQRT_GRP151 : (Group 151 pm_flop) FPU executed FSQRT instruction
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1597 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1622 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
2819 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 351 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
|