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Searched refs:LoadLatency (Results 1 – 21 of 21) sorted by relevance

/external/llvm/include/llvm/MC/
DMCSchedule.h174 unsigned LoadLatency; variable
210 LoadLatency(DefaultLoadLatency), in MCSchedModel()
226 LoadLatency(ll), HighLatency(hl), in MCSchedModel()
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td162 let LoadLatency = 6; // Optimistic load latency assuming bypass.
DPPCScheduleG5.td122 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DPPCScheduleE500mc.td309 let LoadLatency = 5; // Optimistic load latency assuming bypass.
DPPCScheduleE5500.td369 let LoadLatency = 6; // Optimistic load latency assuming bypass.
DPPCScheduleP7.td378 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DPPCSchedule440.td593 let LoadLatency = 5; // Optimistic load latency assuming bypass.
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV4.td198 let LoadLatency = 1;
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td20 let LoadLatency = 3;
DX86SchedSandyBridge.td21 let LoadLatency = 4;
DX86SchedHaswell.td20 let LoadLatency = 4;
DX86Schedule.td634 let LoadLatency = 4;
DX86ScheduleAtom.td535 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
/external/llvm/include/llvm/Target/
DTargetSchedule.td73 // Target hooks allow subtargets to associate LoadLatency and
84 int LoadLatency = -1; // Cycles for loads to access the cache.
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp754 return SchedModel->LoadLatency; in defaultDefLatency()
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td18 let LoadLatency = 4; // Optimistic load latency
DAArch64SchedA53.td23 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DAArch64SchedCyclone.td18 let LoadLatency = 4; // Optimistic load latency.
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td1069 let LoadLatency = 2; // Optimistic load latency assuming bypass.
DARMScheduleSwift.td1080 let LoadLatency = 3;
DARMScheduleA9.td1891 let LoadLatency = 2; // Optimistic load latency assuming bypass.