Searched refs:MSR (Results 1 – 25 of 47) sorted by relevance
12
25 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
22 @ MSR
38 @ MSR
7 ; Check MSR.133 ; Check that multiplications of spilled values can use MS rather than MSR.
246 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
554 MSR = SystemSysRegFixed | 0x00000000 enumerator
1176 case MSR: { in VisitSystem()
2346 case MSR: { in VisitSystem()
1193 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg)); in msr()
1067 MSR{"MS"}
664 MSR = SystemSysRegFixed | 0x00000000 enumerator
1168 case MSR: { in VisitSystem()
1751 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg)); in msr()
58 ; MSR/MRS instructions
116 … minimum:1000 name:PM_EE_OFF_EXT_INT_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off and ext…119 …ounters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off
111 … minimum:1000 name:PM_EE_OFF_EXT_INT_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off and ext…114 …ounters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off
70 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFS…
90 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH…
231 … minimum:1000 name:PM_EE_OFF_EXT_INT_GRP22 : (Group 22 pm_isu_work) Cycles MSR(EE) bit off and ext…234 …ounters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP22 : (Group 22 pm_isu_work) Cycles MSR(EE) bit off
1563 BuildMI(MBB, I, DL, get(AArch64::MSR)) in copyPhysReg()
444 * module/oprofile.[c|h]: Change MSR defines from614 * oprofile.c: don't mask when restoring MSR values
847 * ``MSR``, kernel version: not available to user code.