Searched refs:NON_EXTLOAD (Results 1 – 24 of 24) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 740 NON_EXTLOAD = 0, enumerator
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| D | SelectionDAGNodes.h | 2007 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2015 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 306 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
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| D | MSP430ISelLowering.cpp | 1119 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPostIndexedAddressParts()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZOperators.td | 239 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
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| D | SystemZISelLowering.cpp | 1212 case ISD::NON_EXTLOAD: in isNaturalMemoryOperand()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 1130 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) { in LowerLOAD()
1148 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) { in LowerLOAD()
1184 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32)) in LowerLOAD()
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| D | R600ISelLowering.cpp | 1526 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) || in LowerLOAD()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 518 if (L->getExtensionType() == ISD::NON_EXTLOAD) { in SoftenFloatRes_LOAD()
531 NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, in SoftenFloatRes_LOAD()
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| D | LegalizeVectorOps.cpp | 202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { in LegalizeOp()
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| D | DAGCombiner.cpp | 2729 case ISD::NON_EXTLOAD: B = true; break; in visitAND()
5668 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in ReduceLoadWidth()
5766 if (LN0->getExtensionType() != ISD::NON_EXTLOAD && in ReduceLoadWidth()
5792 if (ExtType == ISD::NON_EXTLOAD) in ReduceLoadWidth()
8030 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { in visitLOAD()
9339 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) in MergeConsecutiveStores()
11074 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { in SimplifySelectOps()
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| D | SelectionDAG.cpp | 4673 ExtType = ISD::NON_EXTLOAD; in getLoad()
4674 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
4724 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
4733 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
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| D | LegalizeDAG.cpp | 533 if (HiExtType == ISD::NON_EXTLOAD) in ExpandUnalignedLoad()
887 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
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| D | TargetLowering.cpp | 1340 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) in SimplifySetCC()
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| D | LegalizeVectorTypes.cpp | 2236 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 625 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 426 assert(LD->getExtensionType() == ISD::NON_EXTLOAD && in LowerLOAD()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 420 LD->getExtensionType() != ISD::NON_EXTLOAD) in isCalleeLoad()
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| D | X86InstrInfo.td | 833 if (ExtType == ISD::NON_EXTLOAD)
851 if (ExtType == ISD::NON_EXTLOAD)
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| D | X86ISelLowering.cpp | 20840 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) { in PerformLOADCombine()
22080 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& in IsDesirableToPromoteOp()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1442 assert(LD->getExtensionType() == ISD::NON_EXTLOAD); in LowerLOADi1()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 918 if (ExtType == ISD::NON_EXTLOAD) in SelectIndexedLoad()
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| D | AArch64ISelLowering.cpp | 1769 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in LowerFormalArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2048 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { in lowerLOAD()
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