| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstrInfo.cpp | 139 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
140 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
145 Address, OffsetReg); in expandPostRAPseudo()
154 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
155 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
161 OffsetReg); in expandPostRAPseudo()
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| D | R600InstrInfo.h | 43 unsigned OffsetReg,
49 unsigned OffsetReg,
224 unsigned OffsetReg) const override;
229 unsigned OffsetReg) const override;
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| D | SIInstrInfo.h | 164 unsigned OffsetReg) const override;
170 unsigned OffsetReg) const override;
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| D | AMDGPUInstrInfo.h | 170 unsigned OffsetReg) const = 0;
178 unsigned OffsetReg) const = 0;
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| D | R600InstrInfo.cpp | 1119 unsigned OffsetReg) const { in buildIndirectWrite()
1120 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1126 unsigned OffsetReg, in buildIndirectWrite() argument
1137 AMDGPU::AR_X, OffsetReg); in buildIndirectWrite()
1151 unsigned OffsetReg) const { in buildIndirectRead()
1152 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1158 unsigned OffsetReg, in buildIndirectRead() argument
1170 OffsetReg); in buildIndirectRead()
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| D | SIInstrInfo.cpp | 1544 unsigned Address, unsigned OffsetReg) const { in buildIndirectWrite()
1553 .addReg(OffsetReg) in buildIndirectWrite()
1562 unsigned Address, unsigned OffsetReg) const { in buildIndirectRead()
1571 .addReg(OffsetReg) in buildIndirectRead()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 168 unsigned OffsetReg; member
220 return Mem.OffsetReg; in getMemOffsetReg()
357 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
366 Op->Mem.OffsetReg = 0; in CreateMEMri()
378 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 471 unsigned OffsetReg = 0; in ReduceLoadStore() local
474 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
502 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
505 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 524 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
525 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 603 unsigned OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
615 .addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| D | MipsISelLowering.cpp | 1914 unsigned OffsetReg = Subtarget->isABI_N64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
1916 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
1919 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1530 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
1537 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 17109 unsigned OffsetReg = 0; in EmitVAARG64WithCustomInserter() local
17165 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARG64WithCustomInserter()
17166 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARG64WithCustomInserter()
17176 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
17187 assert(OffsetReg != 0); in EmitVAARG64WithCustomInserter()
17203 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
17214 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
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